| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 林瑞益 | zh_TW |
| DC.creator | Jui-yi Lin | en_US |
| dc.date.accessioned | 2011-7-15T07:39:07Z | |
| dc.date.available | 2011-7-15T07:39:07Z | |
| dc.date.issued | 2011 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=945401010 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 本論文的目的是設計、分析和實現一個寬頻、低損耗在 0.18 微米互補式金氧半導體製程下的馬遜巴倫，並且証實其可行性。然後我們將這巴倫應用在五個標準互補式金氧半導體製程下的混頻器上。這巴倫是利用一個對稱偏移堆疊多層的結構來實現的。為了得到最小的插入損耗及最大的頻寬，我們提供了一個適當選擇兩條耦合線寬度和耦合線之間偏移寬度的設計準則來達到此目的。對此巴倫所提出的設計步驟可借由電路的實作來相互驗證。量測的結果顯示和理論分析有很好的一致性。比較近年來文獻中所提出不同架構的馬遜巴倫，我們所提出的馬遜巴倫更具有寬頻及低插入損耗等特性。測量兩個單、雙巴倫的頻寬超過 110% 和 90%，並且在 38 GHz 的頻率下其插入損失小於 4.4 dB 和 7.4 dB。並且這兩個巴倫的晶片面積同為 0.07 平方毫米。
我們使用 0.13 微米和 0.18 微米互補式金氧半導體的製程來實現三個被動式電阻混頻器及兩個被動式二極體混頻器。這些使用堆疊式巴倫的混頻器，呈現出寬頻、小面積的特性。這些電阻混頻器展現出超過 14 到 45 GHz (105%)，18 到 54 GHz (100%) 和 28 到 50 GHz （56%）的頻寬。一個 14 到 45 GHz 單平衡電阻混頻器顯現出在7 dBm 的本地振盪器功率下轉換損耗低於 12 dB。這混頻器的本地振盪端到射頻端、本地振盪端到中頻端的隔離度均高於 30 dB。此混頻器晶片面積為 0.53 平方毫米。一個星形混頻器在 18 到 54 GHz 的頻段中，達到低於 12 dB 的轉換損耗，並且在本地震盪頻率從 10 到 60 GHz 下，本地振盪端到射頻端、本地振盪端到中頻端和射頻端到中頻端的隔離度均高於 35 dB。此混頻器的晶片面積為 0.6 平方毫米。ㄧ個次諧波電阻混頻器的轉換損耗從 28 到 50 GHz 的頻率下低於 11 dB。此混頻器的隔離度高於 31 dB且晶片面積為 0.61 平方毫米。兩個二極體混頻器展現出超過 20 到 60 GHz (100%) 和 14 到 52 GHz （115%）的頻寬。單平衡二極體混頻器展現出轉換損耗低於 15 dB 且晶片面積為 0.24 平方毫米。一個星形二極體混頻器展現出在 14 到 52 GHz 的頻寬下轉換損耗低於 15 dB。此混頻器的晶片面積為 0.4 平方毫米。
| zh_TW |
| dc.description.abstract | The purpose of this dissertation is to design, analyze and implement broadband and low-loss Marchand balun in 0.18 um CMOS process to verify the feasibility, and then the balun is used in five passive mixers in standard CMOS technology. The topology of this Marchand balun is utilized a symmetrical offset stack coupled line structure. To achieve a minimum insertion loss and a maximum bandwidth, the design formulas are derived by proper selected the width of coupled lines and the offset width between two coupled lines. The design procedure for the balun is verified by practical implementation. The measured results are agreed with the theoretical analysis. Compare with the literature survey of the recently reported Marchand baluns; the proposed Marchand balun shows the better bandwidth and insertion loss performance. Both single and dual baluns achieve the measured bandwidths of over 110% and 90%, and insertion losses of less than 4.4 dB and 7.4 dB at 38 GHz. These two baluns occupied chip sizes of 0.07 mm2.
Three balanced resistive mixers and two balanced diode mixers are further proposed and implemented in tsmcTM 0.13-um and 0.18-um CMOS processes. These mixers utilized a stack balun feature a wide bandwidth performance with very compact size. The balanced resistive mixers exhibit wide bandwidths over 14-45 GHz (105%), 18-54 GHz (100%) and 28-50 GHz (56%). The 14-45 GHz SBRM achieves a conversion loss of better than 12 dB at 7 dBm of local oscillator (LO) power. The LO to RF and LO to IF isolations are better than 30 dB. The chip area is 0.53 mm2. The star mixer achieves a conversion loss of better than 12 dB from 18 to 54 GHz, and LO to RF, LO to IF and RF to IF isolations better than 35 dB at LO frequencies spanning 10 to 60 GHz. The chip area is 0.6 mm2. The SHPRM has a conversion loss of better than 11 dB from 28 to 50 GHz. The isolations are better than 31 dB and occupy a chip area of 0.61 mm2. Two balanced diode mixers exhibit bandwidths over 20-60 GHz (100%) and 14-52 GHz (115%). The single balanced diode mixer achieves conversion loss lower than 15 dB with compact chip size of 0.24 mm2. The star diode mixer has conversion loss of lower than 15 dB 14 to 52 GHz. The chip size is only 0.4 mm2.
| en_US |
| DC.subject | 互補式金氧半導體 | zh_TW |
| DC.subject | 馬遜巴倫 | zh_TW |
| DC.subject | 混頻器 | zh_TW |
| DC.subject | balun | en_US |
| DC.subject | CMOS | en_US |
| DC.subject | mixer | en_US |
| DC.title | 寬頻與低損耗之堆疊對稱偏移金氧半導體平衡至不平衡轉換器應用於被動型混波器之研究 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Broadband and Low-loss Symmetric Offset Stack CMOS Balun for Passive Mixer Designs | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |