| dc.description.abstract | Ternary content addressable memory (TCAM) is widely used in digital systems, especially for network applications. To support parallel comparison function, however, a TCAM has complex function. The complex function causes that the TCAM becomes an area-consuming and power-consumption component. Therefore, low-area and low-power are two major challenges in designing a cost-efficient TCAM. Also, yield improvement techniques are very important for the TCAM since the area of TCAM is usually very large.
In this thesis, we propose a low-power TCAM with hybrid tree-NAND/NOR match line. The hybrid tree-NAND/NOR structure can increase the number of bits of NAND-type cells in a TCAM word such that the compare power of the word and the compare delay caused by the NAND-type cells can be minimized. Therefore, the energy of compare operation of the proposed TCAM with hybrid NAND/NOR match lines is very low. We have implemented a 32x64-bit TCAM with hybrid NAND/NOR match lines. Measurement results of the TCAM test chip show that the power consumption of the TCAM is only about 0.4122mW at 110MHz. Also, the energy consumption is very low, which is only about 1.90fJ/bit/search. In comparison with the existing TCAMs for general applications, the proposed TCAM achieve better energy consumption.
We also propose a built-in self-repair (BISR) scheme for the TCAM. In the BISR scheme, a programmable built-in self-test circuit is proposed to test the functional faults of the TCAM and a novel reconfiguration mechanism is proposed to swap defective elements. Differing from the widely-used shift redundancy scheme, the proposed redundancy reconfiguration scheme incurs constant delay penalty regardless of the number of implemented redundancies. Experimental results show that the delay and the area cost of the BISR circuit are only about 0.85ns and 21920um^2, respectively. | en_US |