| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 謝維哲 | zh_TW |
| DC.creator | Wei-jer Ross Hsieh | en_US |
| dc.date.accessioned | 2008-7-24T07:39:07Z | |
| dc.date.available | 2008-7-24T07:39:07Z | |
| dc.date.issued | 2008 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=955201008 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 由於高效能與高可靠性的需求，多核心系統設計已成為一種趨勢；而診斷此多核心系統之電路與掃描鏈來提高良率是一個很重要的問題。在本論文中，我們提出一個新的錯誤IP或核心和錯誤測試向量辨識電路，用於自我測試掃描鏈之多核心晶片上；同時提出一個加強掃描鏈診斷方法，用於診斷掃描鏈啟動訊號的錯誤。辨識電路使用多數決電路的概念，在進行晶片內部測試之同時，進行錯誤的評估與比較。而加強掃描鏈診斷方法著重於兩種掃描鏈啟動訊號的錯誤行為：一種是固定在平移模式的錯誤，而另一種錯誤是固定在捕捉模式的錯誤。對固定在平移模式的錯誤，我們提出兩種診測方法：一種是將輸入的測試圖像平移一位元作為模擬錯誤行為圖像進行比較；另一種是直接與正確的核心進行比較。對固定在捕捉模式的錯誤，我們提出使用錯誤字典技術、折合比較評分法、統計分析與簡化過的信號輪廓技術。將錯誤訊息與記錄在錯誤字典中訊息進行比較評分，以找尋可能的錯誤位置，並用統計分析與簡化過的信號輪廓技術補強，比較評分法後，挑出分數太低的錯誤訊息。
實驗結果顯示，我們提出的診斷電路架構不但不會增加太多的面積，卻可大幅降低收集測試資訊所需的時間。在掃描鏈診斷方面，我們診斷固定在平行模式的錯誤方法，對於我們所測試的電路有非常良好的效果；而利用診斷固定在捕捉模式的錯誤方法雖無法達到前者那樣好的效能，但依舊可得到相當不錯的結果。 | zh_TW |
| dc.description.abstract | Multi-core architecture with built-in self-test (BIST) has become a design trend for VLSI chips due to their needs of high performance and high reliability. Efficient approaches for diagnosing fail cores and scan chains thus are imperative for yield enhancement. We propose in this thesis not only a new failing intellectual property and vector identification circuit (FIPVIC) for identifying failing cores and vectors of a scan-BIST multi-core chip but also an enhanced scan chain diagnosis scheme for scan-enable fault. The FIPVIC design uses the concepts of voter of the triple-module-redundancy (TMR) design and on-chip evaluation and comparison to find out which core and vector failed to the BIST test. The enhanced scan chain diagnosis scheme focuses on two diagnoses of scan-enable faults: the stuck-at-shift (SAS) fault and the stuck-at-capture (SAC) fault. In order to diagnose stuck-at shift fault, we propose two diagnosis methods that either use shifting-1-bit process to match the faulty behavior pattern or use direct comparison approach which compares the faulty response with the golden pattern. For diagnosing stuck-at capture fault, we propose a diagnosis method that uses fault dictionary-based diagnosis technique, convolution comparison score technique, statistics analysis, and simplified signal profiling technique. We create the dictionary by storing the scan output responses and use convolution comparison score technique to compare signatures of test response then calculate the score of each fault candidate cells. At last, statistics analysis and simplified signal profiling technique are used to supply for scoring the signature, which gets too low scores in convolution comparison. Experimental results show that the proposed FIPVIC for multi-core chip can efficiently (only took half time of the typical one) identify the failing core and vector with a small amount of area overhead. The proposed diagnosis approach for SAS can very precisely locate the faulty scan cell for most simulated benchmarks. Although the proposed approach for SAC cannot do as well as the approach for SAS, it still get quiet high success rate. | en_US |
| DC.subject | 多核心系統晶片診斷 | zh_TW |
| DC.subject | 掃描鏈診斷 | zh_TW |
| DC.subject | Multi-core Diagnosis | en_US |
| DC.subject | Scan Chain Diagnosis | en_US |
| DC.subject | Scan enable fault | en_US |
| DC.title | 多核心系統晶片之診斷方法 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Diagnosis Approaches for Multi-Core System Chips | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |