| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 林璁輝 | zh_TW |
| DC.creator | Tsung-hui Lin | en_US |
| dc.date.accessioned | 2008-11-16T07:39:07Z | |
| dc.date.available | 2008-11-16T07:39:07Z | |
| dc.date.issued | 2008 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=955201016 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 隨著資料傳輸速率需求的增加，對於輸入與輸出的頻寬限制也與日俱增，因此高速串列傳輸系統逐漸取代傳統的並行傳輸方式，例如應用在乙太網路及光纖網路上的規格，如10G Ethernet、OC-192。著重於有線或是匯流排上的應用有PCI-Express、Serial-ATA…等系統，在這些規格所傳輸的資料速度已達到Gb/s的等級。在串列傳輸系統中，接收端需要有能力擷取輸入資料內嵌的時脈資訊。本論文採用雙迴路架構，利用半速率取樣方式應用於接收端的時脈與資料回復電路，並以應用於Serial-ATA III的規格為目標。
本論文是應用於6Gb/s的串列傳輸系統接收端中，輸出為二組3Gb/s的並行資料。其中雙迴路架構分別由多相位時脈倍頻器與資料回復迴路所組成。其主要優勢在於二個獨立迴路，可以解決單一迴路中抖動轉移函數與抖動容忍度的頻寬互相衝突問題。資料回復迴路接收八組由時脈倍頻器所提供的相位均分時脈，經由bang-bang相位偵測器判斷取樣時脈與輸入資料的相位差異，取樣結果將輸出於數位控制電路以決定相位內插器的權重值，其中相位內插器的解析度平均值近似於5ps，最後資料回復迴路逐步校準時脈成為最佳取樣資料位置。
在半速率取樣時脈資料回復電路實現上，採用UMC 0.09um 1P9M CMOS製程，供應電源為1V，晶片面積為1.03mm2。 | zh_TW |
| dc.description.abstract | As the demands for the data rate increase, the input–output (I/O) bandwidth will progress with each passing day. Therefore, the high speed serial I/O systems have replaced traditional parallel I/O systems gradually. For example, 10G Ethernet and OC-192 are applied in Gigabit Ethernet and Fiber Channel. PCI-Express and Serial-ATA are used in wire or bus serial links. Most of the systems operate at the data rate attending to the level of Gb/s. In the serial link system, the receiver must have the ability to obtain the frequency of clock from the incoming data. This thesis adopts a dual loop clock and data recovery circuit, and utilizing half-rate sample technique in the receiver circuit. It tries fitting the corresponding specification of Serial-ATA III.
A receiver circuit is used in the serial link system with 6Gb/s, and retime them to two group of 3Gb/s parallel output data. A dual loop structure consists of a multi-phase frequency synthesizer and a data recovery loop. The main advantage of two independent loops can solve the problem that bandwidth of jitter transfer and jitter tolerance conflicts each other in the single loop. The data recovery loop receives eight clock signals having equally spaced and uniformly distributed phases from the frequency synthesizer. Then judge the phase difference between sample clock and input data with bang-bang phase detector. The sampling results will be output in digital control circuit to determine the phase interpolator weight value. Among them resolution average of phase interpolator is approximate to 5ps. Finally, the data recovery loop adjusts the clock phase gradually, which becomes the best sample position.
A half-rate clock and data recovery circuit is achieved in UMC 0.09um 1P9M CMOS technology with 1V power supply. The chip occupies an area of 1.03mm2. | en_US |
| DC.subject | 相位內插器 | zh_TW |
| DC.subject | 雙迴路架構 | zh_TW |
| DC.subject | 半速率取樣 | zh_TW |
| DC.subject | 時脈與資料回復電路 | zh_TW |
| DC.subject | dual loop structure | en_US |
| DC.subject | phase interpolator | en_US |
| DC.subject | half-rate sample | en_US |
| DC.subject | CDR | en_US |
| DC.title | 6-Gb/s半速率時脈與資料回復電路設計與實現 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Design and Implementation of 6-Gb/s Half-Rate Clock and Data Recovery Circuit | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |