| dc.description.abstract | Due to the great evolution of LCD panel technology, the requirement for image in high-definition has been indispensable. Thus, for high-end LCD applications, the demands of data rate, memory bandwidth, and access power are drastically increased. With the proposed high speed and efficient embedded image compression codec, the data of image with high resolution and frame rate can be encoded or decoded in real time. Hence the memory bandwidth and the access power can be reduced. The image compression algorithm with lossless/lossy mode is proposed in this paper. With a rate control mechanism in lossy mode, the size of image data is assured. Hence the required capacity of external memory can be greatly reduced. For a target compression ratio, the rate control mechanism adaptively adjusts the quantization parameter according to the image content, and thus a good trade-off can be achieved between visual quality and coding efficiency.
In order to deal with image data in high-definition, the algorithm is designed for VLSI-oriented and maintains a competitive coding efficiency. The proposed embedded compression codec utilizes techniques of efficient data scheduling and pipeline stages to improve processing speed, and image samples can be encode and decode in parallel. The proposed design is implemented in TSMC 0.18um technology with Artisan cell library. With two-level parallelism, the max throughput of 744 Mbyte/sec, power consumption of 226mW@186MHz, core size of 1.58x1.58 mm2, and die size of 2.06x2.07mm2 can be achieved. The proposed embedded codec is fully compatible for Full-HD 1080p@60Hz in RGB domain. In comparison with other existing works, the proposed design is well-behaved in throughput and power consumption, and the cost in area and storage device is reduced. Furthermore, with capacity of flexible parallelism, the hardware architecture can be improved for advanced display specifications, such as QHD and QFHD. | en_US |