| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 陳培炘 | zh_TW |
| DC.creator | Pei-Shin Chen | en_US |
| dc.date.accessioned | 2008-10-9T07:39:07Z | |
| dc.date.available | 2008-10-9T07:39:07Z | |
| dc.date.issued | 2008 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=955201022 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 正交分頻多工(Orthogonal Frequency Division Multiplexing, OFDM)調變技術廣泛的應用於寬頻通訊系統中。電路設計上的重要元件，反離散傅立葉轉換(Inverse Discrete Fourier Transform, IDFT)與離散傅立葉轉換(Discrete Fourier Transform, DFT)電路，無論在演算法、硬體架構上，皆已發展相當長的時間。然而DFT並非唯一的OFDM正交基底，在此我們提出利用離散哈特萊轉換(Discrete Hartley Transform, DHT)取代離散傅立葉轉換之傳輸架構，並使等效通道得以被對角化，接收端可使用一階頻域等化器來做通道等化。利用純實數運算特性，DHT可降低OFDM調變/解調之運算複雜度。
硬體考量方面，本論文提出一個新的DCT-based DHT架構，配合所提出之DHT-OFDM系統，應用於無線區域網路系統之中。在符合標準的規範情況下，本電路僅需操作在20 MHz即可符合IEEE 802.11a/n的系統需求。本論文實現一個64點DHT為基礎之OFDM調變/解調變器，使用SMIMS VeriEnterprise Xilinx FPGA驗證電路功能，並利用0.18-μm製程做實現。晶片核心面積為0.928 0.935 mm2，包含輸出暫存器及除錯電路。晶片操作在20 MHz的頻率、1.8 V電壓下，晶片功率為28.95 mW。 | zh_TW |
| dc.description.abstract | Orthogonal frequency division multiplexing (OFDM) technology has been widely used in wideband communication. The critical component of OFDM system, Inverse Discrete Fourier Transform (IDFT) and Discrete Fourier Transform (DFT), are well defined components due to its regular algorithms and architectures. Since DFT is not the only orthogonal basis for OFDM system, in this thesis, we proposed a new DHT-OFDM to replace the DFT-OFDM. The new architecture can diagonalize the baseband equivalent channel, the other words, the receiver can use a one-tap equalizer to equalize the channel. According to the pure real computation, DHT based OFDM modulator/demodulator can reduce the computing complexity in OFDM systems.
In hardware implementation, we proposed a low hardware cost DCT-based DHT architecture. Combining the proposed DHT-OFDM algorithm, the DHT-OFDM modulator/demodulator is applied to wireless local area network (WLAN). The DHT architecture can operate at 20 MHz meeting IEEE 802.11a/n standard requirements. The proposed 64-point DHT is evaluated by SIMIS VeriEnterprise Xilinx FPGA development board, then the processor is designed in a 0.18-μm CMOS process. The core area is 0.928 0.935 mm2 including the output buffer and debug module. The chip power is 28.95 mW in 1.8 V supply voltage at the clock rate of 20 MHz. | en_US |
| DC.subject | 快速傅立葉轉換 | zh_TW |
| DC.subject | 離散傅立葉轉換 | zh_TW |
| DC.subject | 快速哈特萊轉換 | zh_TW |
| DC.subject | 離散哈特萊轉換 | zh_TW |
| DC.subject | 正交分頻多工 | zh_TW |
| DC.subject | FFT | en_US |
| DC.subject | DFT | en_US |
| DC.subject | FHT | en_US |
| DC.subject | DHT | en_US |
| DC.subject | OFDM | en_US |
| DC.title | 利用實數運算核心之哈特萊轉換OFDM調變/解調變器 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | A Real-valued Computation Kernel DHT-based OFDM Modulator/Demodulator | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |