博碩士論文 955203019 完整後設資料紀錄

DC 欄位 語言
DC.contributor通訊工程學系zh_TW
DC.creator顏健安zh_TW
DC.creatorYen-Chien Anen_US
dc.date.accessioned2009-1-12T07:39:07Z
dc.date.available2009-1-12T07:39:07Z
dc.date.issued2009
dc.identifier.urihttp://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=955203019
dc.contributor.department通訊工程學系zh_TW
DC.description國立中央大學zh_TW
DC.descriptionNational Central Universityen_US
dc.description.abstract本論文最主要的目的是在如何實現建構出具備簡便操作、高彈性的模擬參數範圍、通道效應逼真、成本降低等特點之通道模擬器,並利用Veilog硬體描述語言,實現在FPGA發展板。通道衰減模擬器為通訊系統在設計與認證上,所不可或缺的一項測試工具,其中Jakes 模型由於具備架構簡單、符合電波散射理論並且能夠呈現都卜勒偏移頻率效應等優點,而廣泛的被應用於Rayleigh 衰減通道的模擬。 在OFDM發射器,提出了一可行的OFDM調變方式的FPGA實現方法,並介紹IFFT與循環字首(Cyclic prefix)加入的具體電路。 zh_TW
dc.description.abstractThis paper principal objective is discuess how can channel simulator include easier operation, more flexible parameter choices, more realistic channel effect, and lower cost, and use the Verilog Hardware Description Language to implement a multipath fading channel emulator on FPGA development board. Fading channel simulator is one of the most important testing equipments for the design and identification of communication systems. Jake’s model is widely used on the simulation of a Rayleigh fading channel. In the OFDM Transmitter, an OFDM modulation structure based on FPGA is Presented.The circuits of IFFT and cyclic prefix joining are also present. en_US
DC.subjectJakes 模型zh_TW
DC.subjectFPGA發展板zh_TW
DC.subjectRayleigh衰減通道zh_TW
DC.subject通道模擬器zh_TW
DC.subjectOFDM發射器zh_TW
DC.subject循環字首zh_TW
DC.subjectRayleigh fading channelen_US
DC.subjectChannel Emlatoren_US
DC.subjectOFDM transmitteren_US
DC.subjectCyclic prefixen_US
DC.subjectFPGA development boarden_US
DC.subjectJakes modelen_US
DC.title適用於OFDM系統下之通道模擬器研究與實現zh_TW
dc.language.isozh-TWzh-TW
DC.titleImplementation of Configurable Mobile Multipath FadingChannel Emulator for OFDM Systemen_US
DC.type博碩士論文zh_TW
DC.typethesisen_US
DC.publisherNational Central Universityen_US

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明