| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 簡偉仁 | zh_TW |
| DC.creator | Wei-jen Chien | en_US |
| dc.date.accessioned | 2010-1-14T07:39:07Z | |
| dc.date.available | 2010-1-14T07:39:07Z | |
| dc.date.issued | 2010 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=965201115 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 本論文係應用於超寬頻(Ultra Wideband)系統之前端接收機之K頻段壓控振盪器、雙模注入式鎖頻除頻器，以TSMC 0.18-μm CMOS與TSMC 0.13-μm CMOS製程研製。
第二章介紹兩個Ka頻段的壓控振盪器(VCO)架構，使用TSMC 0.18-μm CMOS製程，其中之一的VCO主要訴求為低功耗與低相位雜訊，電路架構為電感-電容(LC)型VCO，設計負電阻的電流再生利用，將能減少功耗和低相位雜訊的需求。量測結果顯示出，操作電壓VDD為1.5 V下，功率消耗約為2.59 mW，中心振盪頻率約為12.15 GHz，可調範圍約為從12.02到12.33 GHz，相位雜訊在頻偏1 MHz時約為 -113 dBc/Hz，最大輸出功率為-4.9 dBm，優化指數為-190 dBc/Hz。另外一個VCO為設計在鎖相迴路(PLL)電路中，主要訴求為具寬頻和低電壓增益(KVCO)，電路架構為互捕式交錯耦合差動LC型 VCO，並設計2位元開關電容作為切換可調頻率範圍，量測結果顯示出，操作電壓VDD為1.8 V下，功率消耗約為7.538 mW，中心振盪頻率約為12.2 GHz，切頻開關從00 ~ 11的可調頻率範圍約為從11.8 ~ 12.61 GHz，相位雜訊在頻偏1 MHz時約為 -108 dBc/Hz，最大輸出功率為-2.48dBm，優化指數為-180.5 dBc/Hz。
第三章介紹Ku頻段VCO的架構，使用TSMC 0.13-μm CMOS製程。在LC型的共振腔中，電感和可變電容的寄生電阻將產生熱雜訊，影響整體電路相位雜訊的大小，因此，交錯耦合對的MOS，除了提供足夠的等效負電阻外，還可以利用MOS內介於閘級和基板等同一個可變電容，做為共振腔內的電容，選用MOS的高Q值基板電容替代可變電容，將有效降低相位雜訊，又可控制負阻和可變電容的大小，做為可調頻率的範圍。量測結果顯示出，電路的操作電壓於VDD為0.7V下，功率消耗為1.372 mW，中心振盪頻率約為25.6 GHz，可調範圍約為從25.47到25.98 GHz，相位雜訊在頻偏1 MHz時約為-108.8 dBc/Hz；最大輸出功率為-1.93 dBm，整體電路的功率損耗為56.8 mW，優化指數為-196.6 dBc/Hz。
第四章介紹Ku頻段的注入式鎖定除二除頻器架構，使用TSMC 0.18-μm CMOS製程。此除頻器將兩種不同注入架構，組合搭配在一起，其目的為提升兩倍頻訊號，將增加除頻器較寬的鎖頻範圍，選用LC型作共振腔，將可達到低功率的訴求。量測結果顯示出，當電路操作電壓VDD在1.8 V下，功率消耗為2.25 mW，自振頻率範圍約為從6.6 到6.9 GHz。鎖頻時相位雜訊在頻偏1 MHz時約為-137 dBc/Hz；當電壓變化從0-1.8V時，鎖頻範圍約為從12.1到14.3 GHz。最大輸出功率為-6 dBm，優值化指標為7.44。
第五章為結論，討論以上晶片優劣處，並對自己的未來期許和努力方向設計目標。
| zh_TW |
| dc.description.abstract | This thesis presents K-band voltage controlled oscillator (VCO) and injection locked frequency divider (ILFD) circuits which can apple in Ultra Wideband system of front-end receiver. The circuits were implemented in TSMC 0.13-?m and 0.18-?m CMOS technologies.
The thesis is organized as follow, Chapter 1 give the motivation and induction of system applications. Chapter 2 introduces two Ka-band VCOs topologies which were fabricated in 0.18-?m CMOS technology. The first VCO mainly targeted for low power consumption and low phase noise. The circuit topology is an LC-VCO with current reuse technique to reduce power consumption and obtain low phase noise performance. The measured oscillation central frequency is 12.15 GHz with tunable frequency range from 12.02 to 12.33 GHz. The power consumption is 2.59 mW from a power supply of 1.5 V, and -113 dBc/Hz phase noise at 1 MHz offset. The maximum output power is -4.9 dBm. The figure of merit (FOM) is high up -190.7 dBc/Hz. The second VCO is designed for wideband tuning frequency by switch capacitor array. The complementary cross-coupled differential LC-VCO was adopted. Two bits capacitance switch was used to choose the tunable frequency range. The measured oscillation central frequency is 12.2 GHz with a tunable frequency range from 11.8 to 12.61 GHz by using the 2-bit switch control (from 00 to 11). The power consumption is 7.538 mW under a power supply of 1.8 V, and -108 dBc/Hz phase noise at 1 MHz offset. The maximum output power is -2.48 dBm. The best FOM is -180.5 dBc/Hz.
Chapter 3 presents a Ku-band VCO topology which was fabricated in 0.13-?m CMOS technology. The parasitic resistance on the inductor and varactor generate thermal noise, to increase phase noise in the circuit. Therefore, cross-coupled transistors provide the sufficient negative resistance. The VCO circuit utilizes the parasitic capacitance between back and gate as a varactor which is part of LC tank to tune the oscillation frequency. This high Q bulk capacitance provides a good phase noise performance. The measured oscillation central frequency is 25.6 GHz with tunable frequency range from 25.47 to 25.98 GHz. The power consumption is 1.372 mW under a power supply of 0.6 V, and -109.9 dBc/Hz phase noise at 1 MHz offset. The maximum output power is -1.93 dBm. The best FOM is very good up to -196.6 dBc/Hz.
Chapter 4 develops a Ka-band ILFD topology which was fabricated in 0.18-?m CMOS technology. This frequency divider used two different injection paths to enhance the second harmonic which will widen the locking range ILFD. The measured free run frequency of ILFD is 6.6 GHz. The power consumption is 2.25 mW under a power supply of 1.8 V. The phase noise is -137 dBc/Hz at 1 MHz offset which VCO is under injection locked. The locking range is from 12.1 to 14.3 GHz with control voltage tuning from 0 to 1.8 V. The maximum output power is -6 dBm. The FOM is 7.44.
Finally, a brief conclusion is given in Chapter 5.
| en_US |
| DC.subject | 壓控振盪器 | zh_TW |
| DC.subject | 注入式除頻器 | zh_TW |
| DC.subject | K band | en_US |
| DC.subject | CMOS | en_US |
| DC.subject | LC-tank | en_US |
| DC.subject | intrinsic tuning vco | en_US |
| DC.subject | ILFD | en_US |
| DC.subject | millimeter-wave | en_US |
| DC.title | 應用於K頻段之低功耗低相位雜訊壓控振盪器暨Ku頻段雙模注入式除頻器之研製 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Implementations of K band Low Power and Low Phase Noise Voltage Controlled Oscillator and Ku band Dual-mode Injection Locking Frequency Divider | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |