| DC 欄位 |
值 |
語言 |
| DC.contributor | 通訊工程學系在職專班 | zh_TW |
| DC.creator | 鍾華倉 | zh_TW |
| DC.creator | Hua-chang Chung | en_US |
| dc.date.accessioned | 2010-7-14T07:39:07Z | |
| dc.date.available | 2010-7-14T07:39:07Z | |
| dc.date.issued | 2010 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=965303005 | |
| dc.contributor.department | 通訊工程學系在職專班 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | H.264/AVC採用了調適性之內部迴路方塊效應濾波器，以去除方塊邊界的視訊雜訊並改善壓縮效率。本篇論文提出一低功率方塊效應濾波器硬體架構設計，以及採用混合且具有邊界濾波可跳過的機智濾波順序。我們採用一個四階管線式架構，用以加速去方塊雜訊效應的濾波程序，同時所提出的水平方塊邊界跳過濾波程序之架構(HESPA)，具有水平邊界跳過濾波程序的感知機制，不僅可以降低功耗，且可以節省濾波的次數，最高可達到每一個巨區塊(16 x 16) 只需100時脈。此外，我們採用一個合理的邊界濾波順序策略，在不影響標準定義的資料相關性原則之下，使用緩衝器儲存濾波中的暫存資料，以加強中間濾波過程資料的重複使用性，不僅可以增加系統的資料產出量，也可降低功耗。
模擬結果顯示，我們在FPGA上所量得的邏輯功率與Parlak的設計相比([19])，可節省超過34%的功耗。本篇架構是以0.18μm 標準元件庫，在頻率200 MHz下合成出19.8 K的邏輯閘數量，與其它文獻比較起來具有相當的硬體成本競爭優勢。
| zh_TW |
| dc.description.abstract | An adaptive in-loop deblocking filter (DF) is standardized in H.264/AVC in order to reduce blocking artifacts and improve compression efficiency. This thesis proposes the low power DF architecture with the hybrid and intelligent edge skip filtering order. We further adopt a four-stage pipeline to boost the speed of DF process and the proposed Horizontal Edge Skip Processing Architecture (HESPA) offers an edge skip aware mechanism in filtering the horizontal edges that not only reduces power consumptions but also saves the filtering orders up to 100 clock cycles per macroblock. In addition, our architecture utilizes extra buffers to store the temporary data without affecting the standard-defined data dependency by adjusting a reasonable strategy of edge filter order to enhance the reusability of intermediate data. Then, the system throughput can be improved, and the power consumption can also be reduced.
Simulation results show that more than 34% of logic power measured in FPGA can be saved while comparing with Parlak’s design ([19]). Furthermore, the proposed architecture is implemented on 0.18μm standardized cell library, which consumes 19.8 K gates at a clock frequency of 200 MHz which is competitive in the hardware cost comparing with other state-of art literatures.
| en_US |
| DC.subject | H.264 | zh_TW |
| DC.subject | 視訊編碼 | zh_TW |
| DC.subject | 去方塊效應濾波器 | zh_TW |
| DC.subject | FPGA | zh_TW |
| DC.subject | 低功率 | zh_TW |
| DC.subject | 硬體實現 | zh_TW |
| DC.subject | Video Coding | en_US |
| DC.subject | H.264 | en_US |
| DC.subject | Deblocking Filter | en_US |
| DC.subject | FPGA | en_US |
| DC.subject | Low Power | en_US |
| DC.subject | Hardware Implementation | en_US |
| DC.title | H.264/AVC去方塊效應濾波器之低功率架構設計及其硬體實現 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Low Power Architecture Design and Hardware Implementations of Deblocking Filter in H.264/AVC | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |