| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 陳柏翰 | zh_TW |
| DC.creator | Bo-Han Chen | en_US |
| dc.date.accessioned | 2011-1-17T07:39:07Z | |
| dc.date.available | 2011-1-17T07:39:07Z | |
| dc.date.issued | 2011 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=975201003 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 正交分頻多工技術對於克服傳輸通道的頻率選擇性衰減效應以及符碼際干擾具有良好的效果。然而，傳送與接收端間的非同步效應會破壞正交分頻多工系統之正交性，進而引進子載波間干擾，將會大幅降低系統之效能。
本論文著重在估測並解決正交分頻多工系統中的取樣時脈偏移非同步問題。我們利用基於自動增益與載波回復之頻域等化器中的相位誤差量，估測出取樣時脈偏移所造成之相位旋轉，將此訊息經由我們所提出之雙迴路系統架構來補償取樣時脈偏移。除此之外，我們結合了傳統時域等化器與Farrow內插器電路，利用時域等化器中係數收斂完成後即閒置之電路，達到係數內插器之功能。
| zh_TW |
| dc.description.abstract | OFDM system has good ability on resisting frequency selective channel fading and inter-symbol interference (ISI). However, non-ideal effects such as synchronization issue between transmitter and receiver will degrade system performance. The orthogonality of OFDM system is destroyed by introducing inter-carrier interference (ICI).
In this thesis, we focus on estimation and compensation methods of sampling clock offset (SCO) effect in an OFDM system. We can estimate phase rotation caused by SCO with phase error information obtained in auto-gain control and carrier recovery based frequency-domain equalizer (AGC-CR FEQ). Then the SCO effect can be compensated in the proposed dual-loop system architecture. Moreover, the conventional time-domain equalizer (TEQ) and Farrow structure interpolator are combined. We occupy idle circuits after coefficients updating in the TEQ to achieve TEQ coefficients interpolation.
| en_US |
| DC.subject | 正交分頻多工 | zh_TW |
| DC.subject | 時域等化器 | zh_TW |
| DC.subject | 頻域等化器 | zh_TW |
| DC.subject | 取樣時脈偏移 | zh_TW |
| DC.subject | TFO | en_US |
| DC.subject | FEQ | en_US |
| DC.subject | TEQ | en_US |
| DC.subject | OFDM | en_US |
| DC.title | 結合等化與取樣時脈同步雙迴路架構設計 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Joint Equalization and Sampling Clock Synchronization in Dual-Loop Architecture | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |