| dc.description.abstract | Three-dimensional (3D) integration technology using through silicon via (TSV) offers many benefits over 2D integration technology, such as low power, high performance, small footprint, heterogeneous integration etc. 3D integration technology has been used to realize dynamic random access memories (DRAMs) that provides higher memory density and higher performance than modern 2D DRAMs. 3D DRAMs typically have multiple channels to provide more data bandwidth. However, testing and yield are two key challenges of the TSV-based3D DRAMs for the volume production.
In the first part of the thesis, a channel-shareable built-in self-test (BIST) scheme for multi-channel 3D DRAMs is proposed. The BIST scheme is capable of applying test pat-terns and evaluating test responses for multiple channels simultaneously, regardless of the read/write latency differences among the channels. As a result, the proposed BIST scheme can significantly reduce the test time. The simulation results show that the proposed BIST scheme can achieve about 11% test time reduction compared to the existing shared BIST scheme for a two-channel 1G-bit DRAM, by paying only about 0.003% area cost.
In the second part of the thesis, we introduce a point-to-point bus-based IO interface for multi-channel 3D DRAMs. Based on the IO interface, we propose a fault-tolerant scheme to tolerance the defects in IO interface such that the yield of multi-channel 3D DRAMs can be improved. The proposed fault-tolerance scheme uses intra-channel and inter-channel reconfiguration mechanisms to tolerance the defects in TSVs and micro bumps of the IO interface. Also, a fault-location algorithm is proposed to locate the positions of open defects. Furthermore, we design a built-in self-repair (BISR) circuit which can generate the proposed fault-location test algorithm and reconfiguration control signals for 3D DRAMs. Analysis results show that the proposed fault-tolerance scheme can achieve above 23% yield gain compared to the existing inter-channel reconfiguration scheme. The BISR designed with TSMC 65nm LP process technology incurs only about 0.28% hardware overhead for a 3D DRAM with 16 channels in which each channel has 128 bits. | en_US |