| dc.description.abstract | Since the circuit design based on CMOS technology achieves the advantages of low cost and high integration capability. The SoC (system-on-chip) research has being developed with integrating the digital, analog, and RF circuits.
However, the material/device characteristics such as low mobility, low breakdown voltage, and large parasitic capacitance always degrade circuit performance for high-frequency and high-power applications. The substrate effect also influences the large-signal characteristic in the microwave switch design, leading to an inferior power handling capability. In order to improve the problem, a method, body/substrate bias, has been proposed in this thesis. The method also was applied to the asymmetrical and the traveling-wave switches.
An introduction, illustrating the relative research and development of high power CMOS switch, is presented. Three high-power switch designs for 1.9 GHz operation are following. The first switch demonstrates an isolation of 29 dB in TX sub-circuit with using the body switch technique. A NMOS transistor used to be a resistor at body node is designed and simulated with a layout parasitic effect in the second high-power T/R switch design. The measured power handling capability of TX switch exhibits an input 1-dB compression point of 28 dBm. The third switch incorporates a shunt transistor to the gate of RX transistor and uses the body biasing technique with negative bias. The power handling capability can further be improved to 34.2 dBm at 1.9 GHz.
In addition, a traveling-wave switch using a dual-gate transistor is presented. The operating frequency is ranging from 15 to 70 GHz. Based on the theory and the simulation results, the power handling performance can be improved by using dual-gate NMOS transistor in the switch. The measured power handling capability of this traveling-wave switch is about 22 dBm, where it presents 0.3-dB power compression point. The 1-dB power compression point of 24 dBm was also predicted in the simulation.
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