| dc.description.abstract | Over the last 50 years, Si-based complementary metal-oxide-semiconductor (CMOS) technology has advanced closely following Moore’s Laws, which has in turn facilitated the development of information technology era. However, device scaling of integrated circuits has encountered severe challenges in device performance, power consumption and manufacturing costs. Finding appropriate materials and technologies to solve these problems is the top priority in semiconductor industry. In this research, we study and fabricate low interface trap density (Dit) InAs and GaSb metal-oxide-semiconductor capacitors (MOSCAPs), and explore the possibility of using these two materials for next generation n- and p-channel three dimensional transistors. InAs is a narrow bandgap material having high electron mobility, which makes it suitable for low power n-channel transistors. GaSb, on the other hand, has high hole mobility and is a good candidate for low power p-channel devices. However, both InAs and GaSb suffer from high Dit at the oxide-semiconductor interface, which limits the modulation of carriers in the channel. In this study, we investigate three processes, including in-situ, ex-situ, and nitrogen/hydrogen plasma treatments for fabricating InAs and GaSb MOSCAPs, and correlate these treatments with the characteristics of the MOSCAPs.
To avoid the notorious native oxides, which sabotage the electrical characteristics of InAs and GaSb MOSCAPs, in-situ preparation of the samples are carried out by connecting the molecular beam epitaxy (MBE) system with the ALD system via an ultra-high vacuum (UHV) transfer tube. HfO2/InAs MOSCAPs prepared by this method exhibit a Dit of 2.21 × 10E12 cm-2eV-1 at the mid-gap as estimated by conductance method. As for GaSb MOSCAPs, devices fabricated on the Sb-stabilized (1 × 3) surface exhibit a Dit as low as 1.86 × 10E12 cm-2eV-1 near the mid-gap, while the devices fabricated on the Sb-rich (2 × 5) surface exhibit short-circuit behavior. This is attributed to the presence of excessive Sb clusters, which cause island growth during the deposition of dielectric films. A physical model is proposed to explain the mechanism.
Since three-dimensional transistors, such as fin field-effect transistors (FinFETs), nano-sheet transistors (NSTs), and gate-all-around (GAA) MOSFETs, are the mainstream devices, ex-situ processes for fabricating InAs and GaSb MOSCAPs have also been developed. Using chemical solution treatment, optimized trimethylaluminium (TMAl) surface treatment and post metal annealing (PMA) processes, Dit of 1.3 × 10E12 cm-2eV-1 is achieved on HfO2/Al2O3/InAs MOSCAPs and 5.3 × 10E13 cm-2eV-1 on GaSb MOSCAPs.
To further reduce the density of interface states, an ex-situ process consisting of HCl solution chemical treatment and nitrogen plasma treatment has been developed for fabricating HfO2/Al2O3/InAs MOSCAPs, which exhibit a Dit of 7.6 × 10E11 cm-2eV-1 near the mid-gap. The reduction of Dit is attributed to the formation of a nitride layer on the InAs surface. It is also found that hydrogen plasma is much more reactive than nitrogen plasma, and tends to induce indium clusters on InAs surface, resulting in high leakage current. For GaSb MOSCAPs, a sequential treatment by HCl chemical cleaning and nitrogen plasma surface treatment leads to Fermi level pinning at the oxide/GaSb surface. Using HCl chemical cleaning and hydrogen plasma treatment, however, there forms a layer of GaOx on the surface. Subsequent nitrogen plasma treatment then leads to the formation of a GaON layer. HfO2/Al2O3/GaSb MOSCAPs prepared by this sequential plasma treatment process show an Dit of 6.4 × 10E12 cm-2eV-1.
The aforementioned results demonstrate that low Dit and unpinned surface of InAs and GaSb MOSCAPs can be obtained by in-situ processes. Meanwhile, InAs and GaSb MOSCAPs with high capacitance, low leakage, low Dit, and high capacitance modulation can also be fabricated by using ex-situ processes, consisting of chemical solution treatment and plasma treatment in ALD system. These surface treatment techniques can be readily applied to the fabrication of future three dimensional transistors for low power consumption CMOS integrated circuits. | en_US |