| dc.description.abstract | Recently, owning to the requirement of the enormous data storage in the multimedia application, the serial link technique, satisfying with the higher data bandwidth, becomes the popular scheme as well as shows the advantage of low cost. In addition, as the electrical devices increase the operation frequency, the problem of electromagnetic interference (EMI) becomes sever. Thus, the EMI steaming from the concentrated peak energy of the clock generator will interfere with the other equipments. Accordingly, the spread spectrum clock generator (SSCG) is commonly used to reduce the EMI.
A 6-Gb/s, 90-nm transmitter incorporating the three-tap feed-forward equalizer (FFE) is presented for the wire line communication. As the data rate rises up to mutigigabits per second, the impact of the limited bandwidth of the channel on the signal degradation has becoming severe with respect of the I/O buffer design for data transmission. Hence, the induced problem, which is the so-called inter-symbol interference (ISI), is mainly caused by skin effect and dielectric loss of the channel while transmitting the high speed random data. To overcome such issue, this study implements a tree-type parallel-in-serial-out (PISO) serializer, and the three-tap FFE, which consists of the pre-, main-, and post-tap, respectively, to pre-emphasize the serial data at the Tx output. The operation principle of the FFE resembles the FIR filter theory. The FFE pre-distorts the low frequency component of the data stream by the sum of each current weighting, which is controlled by the symbol-spaced data. In other words, such operation seems to pull up the high frequency component of the data in advance. Accordingly, via the predicted channel loss, the eye could be still opened at the Rx terminal. In addition, for the radiation issue of EMI, the 6-GHz phase-compensated SSCG is used to spread the peak power of the transmitted data. Such architecture is composed of DLL and PLL, showing the immunity to out-of-band quantization error and digital noise coupling. Thus, through a 39.36-in FR4 PCB trace with a 16.6-dB loss, the simulated peak-to-peak jitters of the 6-Gb/s, 216-1 random bit data is 35.28 ps (i.e., the eye width is 0.788 UI) at the Rx terminal, as well as the EMI is approximated to 24 dB with a 5000-ppm frequency deviation. The chip core area of the PISO and SSCG occupy 0.07 and 0.13 mm2, respectively. The power consumption are 61.2 mW and 56.2 mW at supply of 1.2 V.
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