| dc.description.abstract | With the raising of operation frequency in system-on-a-chip (SoC), clock skew becomes a more important issue needed to be solved. Phase-locked loop (PLL), delay-locked loop (DLL), and synchronous mirror delay (SMD) are used to deskew clock skew in phase and frequency. Except phase alignment, duty cycle distortion is needed to calibrate for system reliability. And pulse-width control loop (PWCL) stands to suppress clock skew on duty cycle.
This study proposes a 0.8 ~ 1.6 GHz all-digital synchronous pulse-width control loop in a 90-nm CMOS process. Forsaking the conventional analog PWCL being the enormous filter area cost as well as sensitive to the process, voltage, and temperature (PVT) variations, the all-digital PWCL mitigates such issue, and exhibits the digital implementation for the compact size. By doing so, it is desirable to be used for the relative clock generation to calibrate the clock duty in the SoC and DDR applications.
With regard to the wide operating frequency range and duty cycle of the input clock, the proposed all-digital PWCL uses the pulse generator (PG) and frequency detector (FD) to automatically adjust the appropriate pulse width of the clock, conforming to the successful clock transmission through the variable delay line (VDL) under PVT variations. In addition, based on the 5-bit time-to-digital (TDC) and 4-bit successive approximation register (SAR) architecture for the coarse and fine phase locking, respectively, the output phase of VDL aligns to that of replica VDL (RVDL).Thus, the phase difference between VDL’s and RVDL’s tenth phase output would be the one clock period. Thus, when one of VDL and RVDL stage phases is selected by the following MUX, the phase spacing between two clocks could be similar to the pulse width of the period signal. As a result, through the synchronous mirror delay (SMD) synchronizing the external clock input signal, the SR-latch combines two phase-delayed signals, and the available duty cycle is generated. The proposed all-digital PWCL generates the output clock with the duty cycle of 30 ~ 70 % in steps of 10%. Operating at 1.6 GHz clock rate, the simulated peak-to-peak jitter is 8.8 ps. The chip area occupies 0.076 mm2, and the total power consumption is around 26 mW at supply of 1.2V.
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