| dc.description.abstract | As the device shrinking of semiconductor process, the process variation causes the mismatch and wire parasitic effect between elements becomes much more seriously. It also causes high complexity and time-consuming on design circuits. Therefore, layout automation is likely to play a key role in analog circuit design.
The performance of many types of analog circuits, like ADC, DAC, or filters etc., relies on the implementation of accurate capacitor ratio. Besides the elements matching, the circuit yield also suffers from the effect of parasitic capacitances. By considering the parasitic effect between each unit capacitor, several smaller unit capacitors will be parallel connected to replace the whole bigger capacitor to reduce these mismatch effects. In this thesis, a yield-aware capacitor array block creator, called App_CABC, is proposed to generate a capacitor array block. User can produce capacitor array fast and good. By a four-step procedure including initial parameter setting, capacitor placement, capacitor routing, parasitic capacitor and extraction, the capacitor array block will be produced. The router can be not only applied to the case of a pair of two targets but also to the multiple target capacitors. By the conjunction of an array assignment using of spatial correlation feature, three cases are used as examples to demonstrate the assignment-routing flow. The first is a case of two targets with a ratio of 1:1. The second is a case of multiple targets with continuous ratio of 45:16:2:1. The last is a case with exponentially continuous ratio of 8:4:2:1:1. After finishing layout creation, the wire parasitic capacitor will be extracted from Calibre. Finally, the accuracy of capacitor ratio and layout area will be contrasted for the evaluation the satisfaction. | en_US |