| dc.description.abstract | As the process technology progresses, one of the most important issues in analog designs is to achieve accurate capacitance ratios, such as analog-to-digital converters and switched-capacitor circuits. In the manufacturing process of analog integrated circuits, capacitor mismatch is usually caused by process variation. There are two types of capacitor mismatch: systematic and random mismatches. To reduce systematic mismatch, designers usually adopt a symmetry structure, to average the mismatch effects induced by process gradients. Capacitors should be distributed uniformly as possible to overcome random mismatch, which means they should exhibit the highest degree of dispersion.
In this paper, we present a force-directed capacitor placement algorithm to reduce the capacitor mismatch. In the initial placement stage, we use an effective and fast way to generate a symmetric and distributed placement. In force-directed stage, the spatial correlation model is applied to the attractive and repulsive forces to let ca-pacitors equilibrium. Finally, we utilize maximum-weight bipartite matching algorithm to efficiently legalize capacitors. Experimental results show that, compared with an SA-based placement method, ours placement method uses shorter running time to generate a higher dispersion structure, which is effective to reduce random mismatch.
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