| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 吳偲銘 | zh_TW |
| DC.creator | Shi-Ming Wu | en_US |
| dc.date.accessioned | 2012-8-8T07:39:07Z | |
| dc.date.available | 2012-8-8T07:39:07Z | |
| dc.date.issued | 2012 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=995201059 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 在無線收發機當中，低雜訊放大器為一不可或缺的電路區塊。它是射頻前端中之接收鏈最前端的主動電路，其功能為在盡量不增加雜訊的狀況下將輸入訊號放大。接收鏈當中最前端電路的雜訊指數與增益主導了整個接收鏈整體的雜訊表現。因此設計一具有低雜訊指數與高增益的放大器是相當必要的。本論文將探討應用於無線個人區域網路系統之低雜訊放大器設計與實現。
我們設計了兩個低雜訊放大器電路。第一個電路是應用於IEEE 802.15.3c、中心頻為60 GHz之低雜訊放大器，並且透過TSMC 90-nm CMOS製程去實現。此電路採用串疊架構去實現，並在串疊架構中加入一雜訊抑制電感以達到降低雜訊與提升穩定度的功能。該電路在61.4 GHz時具有最佳增益13.4 dB，雜訊指數為6.02 dB，3-dB頻寬為12.4 GHz （54.9–67.3 GHz），功耗為29 mW；雜訊指數之量測最低值出現在67.5 GHz，其值為4.95 dB。電路於60 GHz之輸入P1dB為−9 dBm。
第二個電路為應用於IEEE 802.15.3a超寬頻之可調式低雜訊放大器，且透過WIN 0.15-μm pHEMT製程實現。電路架構採用兩級串接架構去實現，並使用以變容二極體為基礎的可調式匹配網路以達到操作頻率可調的功能。該電路在可調頻率（6.5–8.5 GHz）範圍內，其增益介於6.87–8.3 dB，雜訊指數介於4.4–5.5 dB，電路於7.5 GHz之輸入P1dB為−6 dBm，功耗為16.5 mW。
| zh_TW |
| dc.description.abstract | In wireless transceivers, low noise amplifier (LNA) is an indispensable circuit block. It is the first active circuit in the receiving chain of a radio frequency (RF) front-end. The function of a LNA is to amplify the input signal while keeping the added noise as small as possible. Because the noise performance of a receiver is dominated by the noise figure and the gain of the first few stages, it is therefore necessary to design amplifiers with low noise figure and high gain. In this thesis, the design and implementation of two LNAs for WPAN applications are presented.
The first LNA is designed for IEEE 802.15.3c frequency band, centered at 60 GHz, and is implemented using TSMC 90-nm CMOS process. In this circuit, cascode topology is adopted. Between the common-source and common-gate stages, an inductor is added to reduce the noise figure and enhances the stability of the amplifier. The amplifier has a maximum gain of 13.4 dB at 61.4 GHz with a noise figure of 6.02 dB. The 3-dB bandwidth is 12.4 GHz (54.9–67.3 GHz) and the DC power consumption is 29 mW. Minimum noise figure of 4.95 dB is observed at 67.5 GHz. The input P1dB at 60 GHz is −9 dBm.
The second LNA is designed for IEEE 802.15.3a ultra-wide band (UWB) applications and is implemented using WIN 0.15-μm pHEMT process. The circuit is a two-stage amplifier with varactor-diode-based tunable matching networks to achieve tuning of the operating frequency. In the operating frequency range (6.5–8.5 GHz), the gain ranges from 6.87 dB to 8.3 dB whereas the noise figure is from 4.4 dB to 5.5 dB. The input P1dB at 7.5 GHz is −6 dBm and the DC power consumption is 16.5 mW.
| en_US |
| DC.subject | 低雜訊放大器 | zh_TW |
| DC.subject | 射頻 | zh_TW |
| DC.subject | 可調式 | zh_TW |
| DC.subject | 無線個人區域網路 | zh_TW |
| DC.subject | 60 GHz | en_US |
| DC.subject | tunable | en_US |
| DC.subject | WPAN | en_US |
| DC.subject | LNA | en_US |
| DC.subject | RF | en_US |
| DC.title | 應用於無線個人區域網路系統之低雜訊放大器設計與實現 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Design and Implementation of Low Noise Amplifiers for WPAN Applications | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |