| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 林武慶 | zh_TW |
| DC.creator | Wu-Ching Lin | en_US |
| dc.date.accessioned | 2012-8-27T07:39:07Z | |
| dc.date.available | 2012-8-27T07:39:07Z | |
| dc.date.issued | 2012 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=995201071 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 利用CMOS製程製作之功率放大器因矽基板絕緣度較差且有較小崩潰電壓限制的缺點，使功率放大器有較差的輸出功率及功率增加效率表現。為了改善矽基板絕緣度低所造成的基板損失，本論文設計的功率放大器利用玻璃基板整合被動元件製程(Glass Substrate Integrated Passive Device Process，GIPD)將被動元件製作在具有高絕緣性的玻璃基板上，降低基板損失以提高被動元件的品質因素，並藉由此製程所提供的覆晶方式(Flip Chip)將被動元件與放大器電路整合。
首先利用TSMC CMOS 0.18 μm RF NMOS模型加入寄生效應建立一串疊式元件(Cascode MOSFET)模型，並製作出串疊12組及48組的測試元件，分析此測試元件的直流特性、高頻特性及高頻功率特性，並和模型比較以驗證串疊式元件模型的準確性。
使用此串疊式元件模型並藉由國家晶片中心(National Chip Implementation Center)所提供的玻璃基板整合被動元件製程，將玻璃基板上之被動元件與使用TSMC 0.18 μm CMOS製程製作之驅動/功率放大級串疊式元件晶片利用覆晶封裝技術整合為Class-E及Class-AB功率放大器電路。此電路的主要特色為將被動元件製作於高絕緣度的玻璃基板上，藉此改善被動元件製作於矽基板上所造成的基板損失與避免使用打線造成的寄生電感所產生的寄生效應。Class-E功率放大器驅動級採用鎖模(Mode Locking)技術，功率放大級元件採用串疊架構。Class-AB功率放大器驅動級和功率放大級皆採用串疊架構，以利提供較大的輸出功率。但實際量測到的功率特性和模擬結果比較有差異，此為覆晶用錫鉛球產生的額外寄生效應造成。
| zh_TW |
| dc.description.abstract | The output power and power added efficiency of power amplifiers implemented in standard CMOS are limited due to silicon substrate loss and low quality factor of passive components. This thesis presented CMOS power amplifiers with the matching networks fabricated by glass substrate integrated passive device (GIPD) process. By using GIPD process, it is possible to obtain the improved quality factor of passive components and reduced substrate loss.
First of all, a cascode device model based on TSMC CMOS 0.18 μm RF NMOS with parasitic effect was proposed and investigated with validation of dc, ac, and power characteristics. The cascode arrangement of transistors was used to increase operation voltage and thus higher output power capability. Subsequently, two CMOS power amplifiers using proposed cascode device model and GIPD process were designed and characterized. Class-E and class-AB power amplifiers were studied with single-end input and output but differential operation inside. In the class-E amplifier, the driver stage was implemented by mode-locking methodology and power stage was implemented in cascode. In the class-AB amplifier, transistors in both stages were connected in cascode for maximum output power. The measured power performance was not as good as simulated, the possible cause was from the flip-chip bumps.
| en_US |
| DC.subject | 功率放大器 | zh_TW |
| DC.subject | 串疊元件 | zh_TW |
| DC.subject | Cascode Devices | en_US |
| DC.subject | Power Amplifier | en_US |
| DC.title | 玻璃基板整合被動元件製程之CMOS功率放大器 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | CMOS Power Amplifier Integrated with Passive Devices on Glass Substrate | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |