| DC 欄位 |
值 |
語言 |
| DC.contributor | 通訊工程學系 | zh_TW |
| DC.creator | 徐銘言 | zh_TW |
| DC.creator | Ming-yan Hsu | en_US |
| dc.date.accessioned | 2012-8-4T07:39:07Z | |
| dc.date.available | 2012-8-4T07:39:07Z | |
| dc.date.issued | 2012 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=995203037 | |
| dc.contributor.department | 通訊工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | DVB-T(Digital Video Broadcasting - Terrestrial)是歐洲廣播聯盟(European
Broadcast Union，EBU)所制定的數位電視廣播規格，也是目前我國所採用的數位電視廣播系統。
在本論文中，我們採用目前我國數位電視廣播之規格，設計並且實現DVB-T即時基頻接收機在FPGA實驗板上，此接收機之數位訊號處理模組中，包括了數位降頻器、訊號同步器、快速傅立葉轉換處理器、通道估測器、通道等化器、軟式決策器、訊號解交錯器及通道解碼器。系統架構以Matlab模擬分析後，在效能與硬體複雜度上選取適當之參數及規格後再以硬體實現。首先以Verilog硬體描述語言撰寫，經由ModelSim軟體邏輯驗證及模擬時序後，再以FPGA板做測試及驗證其功能與效能。
| zh_TW |
| dc.description.abstract | DVB-T, which is a Digital Video Broadcasting standard ratifies by European Broadcast Union and an abbreviation for Digital Video Broadcasting-Terrestrial, is the digital video broadcasting standard adopted in Taiwan. In this thesis, we discuss the design and implementation issues of a real-time baseband receiver for DVB-T system with FPGA. The digital signal processing units required for the baseband receiver include digital down converter, signal synchronizer, Fast Fourier Transform processor, channel estimator/equalizer, symbol deinterleaver, soft decision logics, bit deinterleaver, Viterbi decoder and Reed-Solomon decoder.
The algorithm and specification for each digital signal processing unit is first designed with a compromise between the performance and the hardware complexity. Then the hardware is programmed using Verilog hardware description language and logically verified with ModelSim. Finally, the real-time hardware is implemented and verified with FPGA.
| en_US |
| DC.subject | 里徳所羅門碼 | zh_TW |
| DC.subject | 快速傅立葉轉換器 | zh_TW |
| DC.subject | 數位電視廣播 | zh_TW |
| DC.subject | Reed-Solomon code | en_US |
| DC.subject | Fast Fourier Transform Processor | en_US |
| DC.subject | DVB-T | en_US |
| DC.title | DVB-T基頻接收機之FPGA設計與實現 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Design and FPGA Implementation of Baseband Receiver for DVB-T System | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |