| dc.description.abstract | This study aims to develop an IC testing model (DITM) based on a statistical simulation method to evaluate the test yield and quality of IC products. In order to express the manufacturing and testing parameters clearly, we will take the manufacturability (DUT circuit characteristic parameters) into a standard normal distribution as the basis, and then successively express the standardized parameters of other parameters relative to manufacturability and testability. Finally, we use the quality-yield plot to demonstrate the interaction between the manufacturability parameters and the testability parameters. Since the future distribution of IC products cannot be known, we use current product electrical characteristics and product manufacturing technology to estimate future product distribution trends. Hence, we compared the different future test yield (Yt) values as predicted by Miao–Dalal Yield, DITM, and by ITRS. Between the three different estimation methods, it is clear that the above-simulated result indicated that DITM could accurately and effectively predict future test yield (Yt). Since developmental improvements for testing technologies has been slow, it has become a greater challenge for a supplier to determine the use of existing instruments and tools to achieve quality products with zero defects. To improve product quality, several new schemes of duplicate tests (Multiple test method, Repeated test method, and Unbalanced test method) have been proposed to obtain a maximum yield with the desired qualities. This has been done by applying the duplicate testing methodologies described in Table of the International Technology Roadmap for Semiconductors (ITRS). Finally, with the application of the Repeat test methodology to the table of the test protocol described in the 2015 ITRS Roadmap, it shows clearly that in comparison with the traditional test methodology, Repeat testing can indeed promote the result of test yield by 30% or more. | en_US |