面積與最大線長最佳化之類比積體電路 佈局產生器

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姓名

陳進曜(Chin-Yaw Chen) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

面積與最大線長最佳化之類比積體電路佈局產生器
(Area and Maximal Wire-length Optimization of Analog ICs Layout Generator)

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摘要(中)

由於類比電路元件的敏感性，製程技術快速地發展與元件尺寸大幅地縮小，使得考慮佈局之後的電氣效應以及面積變得非常重要。為了減少電氣效應對電路的影響，類比電路設計大多以人工方式產生佈局，雖然使用類比設計自動化搭配工程師的佈局經驗可以取代部分人工，但是眾多的佈局限制仍然是類比設計自動化發展的最大難題。
目前存在許多類比元件擺置的相關文獻，然而同時考慮到繞線的研究卻非常稀少。為了降低製程以及寄生效應對電路佈局產生的影響，一般常利用拓樸限制處理元件之間的不匹配，但繞線仍會對類比元件產生非預期的電氣效應。為了減少繞線對類比元件的影響，最佳的繞線路徑必須避開類比元件，且應避免過長的線長致使額外的電阻和延遲，因此，在擺置的過程中預留足夠的繞線空間並且限制導線的最大線長（maximal wire-length），以確保電路能達到預定的效能規格。
本論文提出一個在擺置階段同時考量繞線空間及限制每一條導線最長線長的類比自動化設計流程，可以完成元件擺置以及繞線結果。擺置過程中首先針對繞線路徑預留通道，接著提出二階段形狀曲線修剪技巧評估線段的最大線長以及面積的因素，產生符合效能規格並且保有較小面積的結果。最後搭配應用延遲決策技術（DDM）產生複數擺置結果，並且符合對稱、鄰近的擺置限制，提供工程師良好且彈性的選擇。

摘要(英)

Due to the sensitivity of analog components, and the size shrink of devices, post-layout electrical effects increasingly impact the circuit performance. In order to reduce the impact of electrical effects on circuits, the layout of analog circuits are mostly generated by manual. Although layouts of partial designs can be done by EDA tools with experience of engineers, to overcome the complex layout constraints and close to the regarded of engineers are the urgent issues.
Although there are many literatures on analog placement, the number of researches on analog placement considering routing is few. In the placement process, though we can use the topology constraints to reduce the mismatch, the unexpected electrical effects will be produced by the routing paths. In order to reduce the electrical effects produced by the routing paths, routing paths must avoid passing through the analog devices, and the maximal wire-length of routing must be shortened. Implying that to preserve enough routing spaces and limit wire-length in the placement stage are needed.
This work presents an analog placement and routing flow to handle the symmetry constraints, to preserve enough routing spaces, and to limit maximal wire-length between devices. Preserving the routing channels first, then using a two-stage curve pruning technology to trade-off between area and maximal wire-length. The flow is based on the deferred decision making (DDM) technique. Using DDM technique cannot only generate non-stochastic solutions, but also provide multiple and flexible solutions for engineers.

關鍵字(中)

★ 類比電路擺置
★ 面積與最大線長最佳化
★ 效能導向
★ 佈局產生器

關鍵字(英)

★ Analog Circuit Placement
★ Area and Maximal Wire-length Optimization
★ Performance Driven
★ Layout Generator

論文目次

摘要 i
Abstract ii
目錄 iv
圖目錄 vi
表目錄 ix
第一章、緒論 1
1-1 類比電路設計簡介 1
1-2 研究動機 3
1-3 問題定義 6
1-4 論文結構 7
第二章、背景知識 8
2-1 類比電路元件擺置 8
2-1-1 匹配 (matching) 8
2-1-2 對稱 (symmetry) 9
2-1-3 鄰近 (proximity) 10
2-2 導線對類比電路之影響 11
2-2-1 可繞性 (routability) 11
2-2-2 導線長度 11
2-3 廣義分割樹 12
2-4 延遲決策技術 15
第三章、相關文獻 16
第四章、演算法流程 21
4-1 樹狀架構建置 22
4-1-1 限制條件分析 22
4-1-2 配對方程式 (score function) 24
4-1-3 廣義分割樹建構流程 29
4-1-4 對稱廣義分割樹建置流程 30
4-2 形狀曲線操作流程 31
4-2-1 形狀曲線保存資訊 32
4-2-2 產生基礎曲線 34
4-2-3 二階段形狀曲線修剪流程 35
4-2-4 預留通道演算法 38
4-2-5 曲線合併及繞線資訊更新 40
4-3 複數結果挑選 42
4-4 元件定位方法 42
4-5 繞線流程 44
4-5-1 繞線範圍限制 44
4-5-2 迷宮繞線 46
第五章、實驗結果及分析 47
5-1 實驗環境 47
5-2 兩級式放大器實驗結果 49
5-3 電流鏡放大器實驗結果 52
第六章、結論與未來展望 55
參考文獻 56

參考文獻

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指導教授

陳泰蓁(Tai-Chen Chen)

審核日期

2013-8-14

推文