以SoPC軟硬體整合方式實現之智慧型監控系統

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姓名

張志豪(Chih-Hao Chang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

以SoPC軟硬體整合方式實現之智慧型監控系統
(Design for an Intelligent Surveillance System based on System-on-a-Programmable-Chip Platform)

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摘要(中)

隨著數位資訊化的演進，社會對監控器的需求量也與日俱增。監視器拍攝的影像傳回監控主機端，在藉由人力監督的方式來達到其監控的目的。隨著監控攝影機數量的增加，單一人力監控數十個監控畫面的方式仍然顯得吃重、且容易因視覺疲勞遺漏重要資訊，為了達成此目的，我們讓攝影機擁有前處理的能力，在智慧監控系統中，如何在多個物件交錯時達到tracking的效果一直是個挑戰，本論文提出一個以Andes Core為基礎的系統晶片設計，主要包含Foreground detection及Connected component labeling硬體加速模組和一個Processor 的System-on-a-Programmable-Chip 智慧監控系統，利用處理器可將所取得的前景資訊做object tracking以及data compression等運算，考慮到攝影機所搭載的處理器能力，本論文提出一個低複雜度物件追蹤演算法，主要以物件外型及中心點特徵來達到連續畫面物件追蹤的能力，即使物件交會或是物件被遮蔽住亦能判斷其位置，達到追蹤的效果，此外更提出object grouping的演算法來解決當物件紋路與背景太過相近而造成的物件破碎問題，Run-length coding 壓縮技術不僅減少labeling的運算時間，更達到了平均98%的壓縮率.

摘要(英)

The digital surveillance system becomes more and more popular in recent years. It attempts to raise amount of high resolution cameras, consequently those systems stupendously increase the computational load on central server. As in the intelligent object recognition processing flow, the technique on segmentation and tracking multiple targets, such as tracking group of people through occlusion is still challenging. In this paper, we present a hardware design for the intelligent surveillance system. We have a complete system-level solution on algorithm and VLSI implementation. We evaluate the behavior of the moving objects with adaptive search method. We provide the method to track the moving people in successive frame by object boundary box and velocity without color cues or appearance model. Even though people are interacted with each other or the occlusion is caused by other foreground objects, the proposed algorithm can still perform well. Furthermore we consider the distance with camera as an adaptive search range to deal with the people movement issue. As the foreground is similar to the background, the proposed algorithm can still detect the object well. We also propose an embedded data compression technique which not only reduces the computational complexity but also achieves high compression rate. The overall system is developed in a platform-based system-on-a-Programmable-Chip (SOPC) as a demonstration result. As a VLSI implementation result, the logical gate count occupies 139.890 K and the throughput of foreground detection is 6403 K pixels.

關鍵字(中)

★ 監控系統
★ 前景切割
★ 物件追蹤＿
★ 連通物件標記

關鍵字(英)

論文目次

摘要....................................................i
Abstract...............................................ii
Table of Contents......................................iv
List of Figures........................................vi
List of Tables.......................................viii
Chapter 1 Introduction.................................1
1.1 Motivation......................................1
1.2 Foreground Segmentation Overview................7
1.3 Object Tracking Overview........................5
1.4 Thesis Organization.............................7
Chapter 2 Overall of the Proposed Intelligent Surveillance System.....................................8
2.1 Foreground Detection...........................10
2.1.1. Algorithm of Multi Background Maintain.........10
2.1.2. MBM Hardware Accelerator.......................12
2.2 Connected Component Labeling...................14
2.2.1. Algorithm of Object Labeling...................14
2.2.2. Object Labeling Hardware Accelerator...........17
2.3 Object Grouping................................19
2.3 Object Tracking................................20
2.3 Data Compression...............................27
Chapter 3 Architecture Design for Intelligent Surveillance System....................................28
3.1 The Proposed SOPC Architecture.................28
3.2 The Schedule of Proposed System................30
Chapter 4 Implementations and Experimental Results .......................................................33
4.1 Result of Foreground Detection with Connected Component Labeling.....................................33
4.2 Result of Object Tracking......................35
4.3 Result of Data Compression.....................38
4.4 Chip Specification.............................40
4.5 Implementations on SOPC Platform...............43
Chapter 5 Conclusion..................................45
References.............................................47

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指導教授

蔡宗漢(Tsung-Han Tsai)

審核日期

2014-12-2

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