可應用於高溫操作之鍺量子點單電洞電晶體之製程開發與評估

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姓名

劉昱宏(Yu-hung Liu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

可應用於高溫操作之鍺量子點單電洞電晶體之製程開發與評估
(Process Development and Evaluation of Germanium Quantum Dot Single Hole Transistor for High-temperature Operation)

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摘要(中)

隨著 CMOS 關鍵製程技術不斷微縮，現今已快接近物理的極限，因此許多奈米元件越來越受到重視，其中單電子/電洞電晶體結合了小尺寸、高操作速度與低消耗功率等優點，所以單電子/電洞電晶體為大家所矚目的元件之一。本論文致力於關鍵製程模組開發與評估，將其應用於可在高溫下操作之單電洞電晶體。欲製作出在高溫下操作之單電洞電晶體，最關鍵之處在於鍺量子點尺寸及位置上地控制以及如何精準地控制三端介電層的薄膜厚度。
因在關鍵製程模組開發上遇到一些瓶頸，導致元件最後無法順利完成。故藉學長所製作出”利用氮化矽作為穿隧接面之鍺量子點單電洞電晶體”來學習電性量測與分析，以及更進一步地利用此元件做脈衝量測分析，來觀察電洞進出鍺量子點的傳輸行為模式及元件的操作速度，期望未來可應用於高頻元件發展上面。

摘要(英)

As the dramatic scaling of key modules of CMOS technology, the feature sizes of Si CMOS devices are close to their physical limitation. Therefore, nano-devices attract more attentions in nowadays. Single electron/ hole transistors (SETs/SHTs) combine the potentials of small dimension, high operating speed and low power consumption. Thereby, SETs/SHTs become one of the devices that people look forward to. This thesis dedicates and focuses on the process development and evaluation of Ge QD SHT for high-temperature operation. The key modules of SHT for high-temperature operation are the precise control of Ge QD size, position and the dielectric thickness between gate, source, and drain electrode.
Due to the bottleneck of process development, the SHTs could not be realized. Thereby, this thesis used the devices of a senior’s project—“Fabrication and Electrical characterization of Germanium QD Single Hole Transistor with Si3N4 tunnel junction” to learn the measurement and characteristics of SHTs. Moreover, this thesis also characterized the operation speed and transportation mechanism of holes into a Ge QD using a pulse measurement for high-frequency applications in future work.

關鍵字(中)

★ 鍺量子點
★ 單電洞電晶體
★ 選擇性沉積

關鍵字(英)

★ Ge QD
★ single hole transistor
★ selective deposition

論文目次

目錄
第一章簡介 1
1-1 單電子/電洞電晶體的發展 1
1-2 單電子/電洞電晶體的應用 3
1-3 單電洞電晶體操作原理 3
1-4 研究動機 5
1-5 論文概要 6

第二章單電洞電晶體初步製程流程設計 12
2-1 前言 12
2-2 單電洞電晶體初步製作流程 12

第三章元件關鍵製程模組開發 21
3-1 前言 21
3-2 控制鍺量子點尺寸及位置模組開發 21
3-2-1 回顧本實驗室量子點形成方法與定量定位 21
3-2-2 直徑10 nm 以下鍺量子點製作 23
3-2-3 如何控制鍺量子點形成之位置 24
3-3 自我對準式源/汲極模組開發 26
3-3-1 前言 26
3-3-2 複晶矽鍺選擇性沉積 27
3-3-3 製作間隙壁來防止複晶矽鍺成核於氮化矽側壁上 29
3-4 如何精準控制三端氧化層的薄膜厚度 30

第四章元件電性分析與討論 46
4-1 前言 46
4-2 回顧元件 DC 直流特性 46
4-2-1 量測儀器與方法 46
4-2-2 元件參數萃取 47
4-2-3 元件之 DC 直流特性 47
4-3 元件之脈衝量測與特性分析 48
4-3-1 量測儀器與方法 48
4-3-2 如何設定脈衝量測條件 49
4-3-3 脈衝量測結果與討論 49

第五章結論與未來展望 57

參考文獻 58

參考文獻

參考文獻
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指導教授

李佩雯(Pei-wen Li)

審核日期

2014-8-14

推文