基於自適性稀疏表示之影像顯著度偵測系統超大型積體電路設計

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姓名

林彥宇(Yan-yu Lin) 查詢紙本館藏

畢業系所

資訊工程學系

論文名稱

基於自適性稀疏表示之影像顯著度偵測系統超大型積體電路設計
(VLSI Architecture Design for Saliency Detection Based on Self-adaptive Sparse Representation)

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摘要(中)

本篇論文提出了一個高效能的VLSI架構來實現基於自適性稀疏表示的影像顯著度偵測系統。顯著度偵測是一項建立在人類視覺系統上的重要技術，在本論文中將此系統分為兩個處理階段：特徵表示階段與顯著度測量階段。此二階段在顯著度模型上皆是相當重要的研究課題，如何提出較好的特徵表示法及適當的顯著度測量法更是視覺顯著度模型中的核心問題。在眾多的研究中，稀疏表示已經能夠正確地表示出一個信號的重要部分，所以本研究在特徵表示的選擇上使用稀疏表示法。
在系統流程中，特徵表示階段利用K-SVD演算法來找出資料的稀疏特徵，而在顯著度測量階段利用每個稀疏特徵找出其Background Firing Rate (BFR)，再以Feature Activation Rate (FAR)完成此Bottom-up顯著度偵測系統。
本論文所提出的晶片設計中包含了一個K-SVD模組、一個OMP模組、一個BFR模組和一個FAR模組。晶片的電路設計實現於TSMC 90 nm CMOS Technology，整體的晶片面積約為2.42×2.42 mm2。

摘要(英)

This work proposes an efficient VLSI architecture to perform saliency detection based on sparse representation approach. Saliency detection is a very important technology in the human visual system. Representation and measurement are two important issues for saliency models, and good representation is a critical issue in modelling visual saliency mechanism. Sparse representation has been shown to correctly represent an important part of the signal in a number of studies. This paper utilizes K-SVD algorithm for the feature representation stage, and in saliency measurement stage, background firing rate (BFR) is for each sparse feature and then feature activation rate (FAR) completes the bottom-up saliency detection. The proposed chip comprises a K-SVD module, an OMP module, a BFR module, and a FAR module. The prototype chip is a semi-custom chip that is fabricated using TSMC 90 nm CMOS technology on a die with a size of approximately 2.42x2.42 mm2.

關鍵字(中)

★ 稀疏表示
★ K-SVD
★ 顯著度偵測

關鍵字(英)

論文目次

摘要 ii
Abstract iii
圖目錄 iv
表目錄 vi
章節目次 vii
第一章緒論 1
1.1 前言 1
1.2 研究動機與目的 1
1.3 論文架構 2
第二章顯著度偵測簡介與相關研究 4
2.1 簡介(Introduction) 4
2.2 顯著度偵測相關研究 4
第三章基於自適性稀疏表示偵測演算法 6
3.1 基於自適性稀疏表示偵測演算法流程 6
3.2 特徵表示階段 9
3.3 顯著度測量階段 9

第四章顯著度偵測系統之架構設計 11
4.1 系統架構 11
4.2 K-SVD 12
4.2.1 OMP Unit 17
4.2.2 Matrix Multiplieration Acceleration Unit 22
4.2.3 Omega & Error Unit 25
4.2.4 SVD Unit 26
4.2.5 Selection Unit 31
4.3 BFR Unit 32
4.4 FAR Unit 33
第五章實驗結果 35
5.1 電路環境設置 35
5.2 軟體與硬體之實作及比較 39
5.3 電路的合成與Layout 42
第六章結論及未來研究方向 47
6.1 總結 47
6.2 未來研究方向 47
參考文獻 49

參考文獻

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指導教授

王家慶(Jia-ching Wang)

審核日期

2014-8-21

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