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姓名 劉家華(Jia-hua Liu)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 多層次連線架構下考慮優化最大延遲之避免天線效應的金屬層分配方法
(Antenna-Avoidance Layer Assignment Considering Maximum-Delay Optimization under Multi-Tier Interconnect Structure)
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摘要(中) 隨著超大型積體電路製程的快速演進,電路繞線的問題也愈趨龐大,不僅讓連線間的延遲 (interconnect delay) 影響到整個電路的時序,天線效應 (antenna effect) 降低製造良率 (manufacturing yield) 的現象也越來越明顯。在實體設計階段 (physical design),如何最佳化所有連線中最大的延遲,同時避免天線效應的影響,已成為十分重要的課題。
現今已有大量的金屬層分配 (layer assignment) 相關文獻,但其中絕大部分皆沒有考慮每層金屬層之間的相關特性,這將會影響每層金屬層中每條線段 (wire segment) 的容量 (capacity),以及暴露天線的面積 (antenna expose area)。因此,本篇利用現有的文獻去做改良,使之可以在多層次連線架構 (multi-tier interconnect structure) 下,產生符合天線規則的金屬層分配結果,並且將連線間的延遲資訊帶入目標函式 (object function),進而優化 (optimize) 連線間的延遲。實驗結果顯示,本篇所提出之改良的方法,可以很明顯地降低天線違反的導線 (antenna violation net),並且大部分的結果可以在滿足天線規則以及導線擁擠度限制 (wire congestion constraints) 的情況下,優化最大的延遲。
摘要(英) With the evolution of VLSI process, the problem size of ASIC routing grows fast. Besides the timing issue from the interconnect delay, the yield loss due to antenna effect is more and more obvious. As a result, simultaneously optimizing the maximum delay and avoiding the antenna effect is an important issue in physical design.
Although there are a lot of layer assignment works in the literatures, most of them did not consider the layer dependent characteristics, which induce different routing capacities and antenna expose area in each metal layer. Therefore, based on an existing work, some enhancements are made to obtain an antenna-free assignment under multi-tier interconnect structure in this thesis. The interconnect delay is also considered in the object function to optimize the maximum delay. Experimental results showed that the proposed method can reduce the number of antenna violations significantly. In most of the benchmark circuits, the maximum delay is also optimized while satisfying the antenna rules and wire congestion constraints.
關鍵字(中) ★ 金屬層分配
★ 天線效應
關鍵字(英) ★ Layer Assignment
★ Antenna Effect
論文目次 摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vii
表目錄 ix
1 第一章、緒論 1
1-1 天線效應 1
1-2 天線效應的影響 2
1-3 天線效應規則 (Antenna Rule) 3
1-4 天線效應避免 (Antenna Avoidance) 4
1-5 連線延遲 4
1-6 研究動機 5
2 第二章、背景知識 6
2-1 電荷分享 (Charge Sharing) 6
2-2 違反全域天線規則 (Global Antenna Violation) 6
2-3 違反局部天線規則 (Local Antenna Violation) 7
2-4 分隔器 (Separator) 7
2-5 導線擁擠度限制 (Wire Congestion Constraints) 8
2-6 延遲模型 (Delay Model) 9
2-7 相關研究 9
2-7-1 繞線樹分隔 (routing tree partitioning) 9
2-7-2 動態規劃 (dynamic programming) 13
2-8 問題定義 17
3 第三章、多層次連線架構下考慮最大延遲優化之避免天線效應的金屬層分配 19
3-1 演算法流程 19
3-2 多層次連線架構的考量 21
3-3 改善方式 23
3-3-1 違反天線規則偵測 23
3-3-2 最大延遲優化 26
3-3-3 針對多層次連線架構降低執行時間 27
4 第四章、實驗結果與討論 29
4-1 工作平台與實驗說明 29
4-2 實驗結果 31
5 第五章、結論與未來展望 36
6 參考文獻 37
參考文獻 [1] Chih-Chien Lin, Wen-Hao Liu, Yih-Lang Li, “Skillfully diminishing antenna effect in layer assignment stage,” in Proceedings of International Symposium on VLSI Design, Automation and Test, pp. 1–4, April 2014.
[2] Di Wu, Jiang Hu, and Rabi N. Mahapatra, “Antenna avoidance in layer assignment,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 4, pp. 734–738, April 2006.
[3] Gabriel, Calvin T. and de Muizon, E. , “Quantifying a simple antenna design rule,” in Proceedings of International Symposium on Plasma process-induced Damage, pp. 153–156, May 2000.
[4] Hiroshi Shirota, Toshiyuki Sadakane, Masayuki Terai, and Kaoru Okazaki, “A new router for reducing ”antenna effect” in ASIC design,” in Proceedings of IEEE Custom Integrated Circuits Conference, pp. 601–604, May 1998.
[5] Hyungcheol Shin and Chenming Hu, “Thin gate oxide damage due to plasma processing,” Semiconductor Science and Technology, pp. 463–473, November 1996.
[6] ISPD2008全域繞線競賽http://archive.sigda.org/ispd2008/contests/ispd08rc.html
[7] Nangate 45nm open cell library, http://www.nangate.com, 2011.
[8] Prashant Saxena and Chung-Laung Liu, “Optimization of the maximum delay of global interconnects during layer assignment,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 4, pp. 503-515, April 2001.
[9] Sheqin Dong, Jianchang Ao, and Fuqi Luo, “Delay-Driven and Antenna-Aware Layer Assignment in Global Routing under Multi-tier Interconnect Structure,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 5, pp. 740–752, May 2015.
[10] Sukhamay Kundu and Jayadev Misra, “A linear tree partitioning algorithm,” SIAM Journal on Computing, pp. 151–154, March 1977.
[11] Tsung-Hsien Lee and Ting-Chi Wang, “Congestion-constrained layer assignment for via minimization in global routing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 9, pp. 1643–1656, September 2008.
[12] Tsung-Hsien Lee and Ting-Chi Wang, “Simultaneous antenna avoidance and via optimization in layer assignment of multi-layer global routing,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 312–318, November 2010.
[13] W.C. Elmore, “The transient response of damped linear networks with particular regard of wideband amplifiers,” J. Appl. Phys, 19(1):55-63, 1948.
[14] Wen-Hao Liu, and Yih-Lang Li, “Negotiation-based layer assignment for via count and via overflow minimization,” in Proceedings of IEEE/ACM Asia South Pacific Design Automation Conference., pp. 539–544, Jan 2011.
[15] Wen-Hao Liu, and Yih-Lang Li, “Optimizing the Antenna Area and Separators in Layer Assignment of Multilayer Global Routing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 4, pp. 613–626, April 2014.
[16] Yen-Jung Chang, Yu-Ting Lee, and Ting-Chi Wang, “NTHU-Route 2.0: A Fast and Stable Global Router,” in Proceedings of International Conference on Computer Aided Design, San Jose, CA, USA, pp. 338–343, November 2008.
指導教授 劉建男、陳泰蓁(Chien-nan Liu Tai-chen Chen) 審核日期 2015-8-17
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