以戴爾他模型為基礎的漸進式電路壽命分析技術

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姓名

何思蓉(Si-Rong He) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

以戴爾他模型為基礎的漸進式電路壽命分析技術
(An incremental simulation technique based on delta model for lifetime yield analysis)

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摘要(中)

當積體電路製程尺寸越來越小，元件中因老化(aging)現象所導致的參數改變對良率的影響也越來越嚴重，常常使得電路效能(performance)不如預期，甚至會讓電路在一段時間之後就無法正常工作，因此設計電路時，更需要將電路老化的分析加入標準的流程之中，提升產品出廠後的可靠度。然而在傳統的老化分析中，需在模擬時間與準確度之間做取捨，若以模擬時間為考量，通常會直接以出廠時的參數來推估老化後的參數，然而在老化的過程中，電路的參數會跟著不停的變動，若是沒有更新這些參數，將使得老化分析結果不夠準確；若以準確度為考量，在分析過程中不斷更新電路參數，雖然可以得到準確的分析結果，卻需要非常多次的模擬才能完成，而花費相當多的時間。
為了改善現今老化分析的準確度以及模擬速度。本論文提出一個以戴爾他模型為基礎的漸進式電路壽命分析技術，最大的特點在於老化分析時，使用漸進式(incremental)的方式來更新老化所導致的參數改變，以保持電路老化分析的精準度，另外再加上戴爾他模擬(delta simulation)的方式來加快模擬的速度，以達到最佳的效能。由實驗結果觀察可知，本論文所提出的方法確實有效提升了分析速度，也能同時保持老化分析的精準度，是ㄧ個兼顧效能與準確度的好方法。

摘要(英)

With the advance of VLSI technology, the parameter shift due to device aging has increasingly impacts on circuit yield. The aging effects may degrade circuit performance and cause circuit failure after a period of time. As a result, aging analysis is necessary in standard design flow to improve product reliability. Previous works of aging analysis have to find a trade-off between accuracy and simulation time. In order to reduce the simulation time, most of the previous works estimate the degraded device parameters based on the fresh design. However, the device parameters keep change during the aging process. If those parameters are not updated during the aging analysis, some errors will exist in the analysis results. In order to obtain accurate results, some analysis approaches try to continuously update the device parameters in the analysis procedure. Although the accuracy of estimation results is improved significantly, a lot of simulation time is required due to the huge number of simulations.
In order to improve the accuracy and simulation speed of the aging analysis, this thesis proposes an incremental simulation technique based on delta model. This approach adopts incrementally updated device parameters during aging analysis to keep high accuracy. Furthermore, delta simulation concept as well as the dynamic aging sampling are adopted to reduce the simulation time. As demonstrated in the experimental results, the proposed approach is an effective way to obtain high speed-up and keep estimation accuracy.

關鍵字(中)

★ 壽命良率分析
★ 電路老化
★ 戴爾他模擬
★ 漸進式
★ 蒙地卡羅統計

關鍵字(英)

論文目次

摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vi
表目錄 viii
第一章、緒論 1
1.1 研究動機 1
1.2 相關研究 5
1.2.1 Berkeley Reliability Tool (BERT) 5
1.2.2 Cadence RelXpert 6
1.2.3 ELDO 7
1.2.4 依比率預測老化參數之方法 8
1.3 論文結構 10
第二章、背景知識 11
2.1 電路老化的成因 11
2.1.1 熱載子注入 12
2.1.2 絕緣崩潰 14
2.1.3 電子遷移 14
2.1.4 負偏壓溫度不穩定性 15
2.2 統計分析方法 16
2.2.1 降低時間點所需的樣本數量 17
2.2.2 壽命良率分析之概念 19
2.2.3 所使用的電路老化模型 20
第三章、漸進式老化分析方法 22
3.1 戴爾他電路 22
3.1.1 戴爾他電路概念 22
3.1.2 戴爾他電路之電路參數 25
3.2 用於電路老化的漸進式分析方法 29
3.2.1 電路老化的漸進式分析之概念 29
3.2.2 動態取樣分析之概念 32
3.2.3 漸進式電路老化分析之流程圖 33
第四章、實驗結果 35
4.1 二階NMOS放大器 35
4.1.1 漸進式分析方法 36
4.1.2 漸進式分析加上戴爾他模擬 37
4.1.3 蒙地卡羅統計分析 38
4.2 Voltage Bandgap Reference電路 41
4.2.1 漸進式分析方法 41
4.2.2 漸進式分析加上戴爾他模擬 43
4.2.3 蒙地卡羅統計分析 44
第五章、結論 47
參考文獻 48

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指導教授

劉建男

審核日期

2017-1-20

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