自動辨識混合訊號電路中構成區塊及RLC元件之方法

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：24

、訪客IP：3.15.11.212

姓名

王俊(Chun Wang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

自動辨識混合訊號電路中構成區塊及RLC元件之方法
(Automatic Recognition of Building Blocks and RLC Components in Mixed-Signal Circuits)

相關論文

★ 用於類比電路仿真之波動數位濾波器架構的自動建構方法	★ 使用波動數位濾波器與非線性MOS模型的類比電路模擬平台
★ 實現波動數位濾波器架構下之類比仿真器的非線性電晶體模型	★ 以節點保留方式進行壓降分析中電源網路模型化簡的方法
★ 以引導式二階權重提取改進辨認二階臨界函數之研究	★ 用於類比電路仿真器的波動數位濾波器架構之定點數實現方法
★ 以基本類比電路架構為基礎的佈局自動化工具	★ 可保留設計風格及繞線行為之類比佈局遷移技術
★ 自動辨識混合訊號電路中數位區塊之方法	★ 運用於記憶體內運算的SRAM功率模型之研究
★ 考量可繞度及淺溝槽隔離效應之類比佈局擺置微調方法	★ 一個適用於量化深度神經網路且可調整精確度的處理單元設計: 一種階層式的設計方法
★ 一個有效的邊緣智慧運算加速器設計: 一種適用於深度可分卷積的可重組式架構	★ 實現類比電路仿真的波動數位濾波器架構生成與模擬
★ 用於類比電路仿真器的波動數位濾波器之硬體最佳化方法	★ 以波動數位濾波器實現類比電路仿真器所需的FPGA表格縮減技術

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

隨著電路製程的演進，混合訊號系統的積體電路設計變得越來越複雜，加速類比與數位混合訊號模擬的時間，是現在驗證單晶片系統設計中很重要的一環，以硬體描述語言建立類比電路的行為模型，是一種有效率的混合訊號系統驗證方式，為了將設計者的電路自動轉換成行為模型，在本論文中提出一套有效率的電路架構分析流程，可以自動從電路規格或連線關係萃取出混合訊號設計中的構成區塊，被動RLC元件將辨識獨立出來，有利于電晶體的辨識與轉換，且建構出一個架構分析平台，將Netlist檔案自動轉換成Verilog檔案，將設計的層級從電晶體層級拉到行為階層，達到加速混合訊號系統電路模擬的效果且有效地協助設計者減少額外工作時間，由幾個電路上的實驗結果來看，我們所提出的自動辨識平台確實能夠正確辨識出對應的電路，並維持模擬結果的準確度。

摘要(英)

The design and development of analog/mixed-signal (AMS) integrated circuits is becoming increasingly complex as technologies advances. Speeding up analog and mixed signal simulation is becoming more important in SoC design verification. Modeling analog circuit blocks by hardware description language and building their behavioral models is an efficient approach for verifying AMS systems. To transform any designer circuits into their respective behavioral models automatically, in this thesis, we proposed an efficient structure analysis flow that can extract building blocks in mixed-signal design automatically based on given circuit specifications and netlist. Moreover, passive RLC components within the circuits are analyzed independently and then removed from the circuits before the transistor structure analysis and transforming processes. This is accomplished by a structure analysis platform for transforming Spice Netlist files into Verilog automatically, and transforming transistor-level design into behavior-level design. Achieves the purpose of speeding up AMS system simulation and reduces verification time and complexity for designers. As shown in the experimental results on several circuits, the proposed approach is able to achieve correct recognition of the respective given circuits instantaneously.

關鍵字(中)

★ 辨識
★ 混合訊號

關鍵字(英)

★ recognition
★ mixed-signal

論文目次

摘要 v
Abstract vi
致謝 vii
Contents viii
List of Figures x
List of Tables i
Chapter One: Introduction 1
1- 1 Motivation 1
1- 2 Problem Formation 7
1- 3 Outline 8
Chapter Two: Background Information 9
2- 1 Spice Netlist Format 10
2- 2 Graph Representation 12
2- 3 Related Works 14
2-3-1 SubGemini 14
2-3-2 Resource Management 16
2-3-3 DC Connect Component Partition Method 18
Chapter Three: Structure Analysis and Verilog File Generation Platform 20
3- 1 Structure Analysis and Verilog File Generation Platform Flow 20
3- 2 Pre-processing Work 22
3-2-1 Uniform device name 23
3-2-2 Encode 25
3- 3 Top-Down Screen Analysis 28
3-3-1 Sub-circuit Structure Analysis 30
3-3-2 DC Connect Analysis 33
3-3-3 Vertical Grouping for Analog Structure Analysis (VGFA) 37
3-3-4 Horizontal Grouping for Analog Structure Analysis (HGFA) 40
3- 4 Output Verilog File 42
Chapter Four: RLCD Components 44
4- 1 RLCD Components Analysis 44
4- 2 RLCD Components Encoding Rules 46
4- 3 RLCD Components Removal 49
Chapter Five: Experimental Results 51
5- 1 Structure Analysis of a Two Stage OPA 51
5- 2 Structure Analysis of a Phase Lock Loop (PLL) 55
5- 3 Parallel-in/Serial-out System Simulation Results and Time Analysis 57
Chapter Six: Conclusion and Future Works 60
References 61

參考文獻

[1] http://www.cadence.com/eu/Documents/MicrosoftPowerPoint-ToT2013openend.pdf
[2] https://verificationacademy.com/verification-horizons/october-2012-volume-8-issue-3/improving-analog-mixed-signal-verification-productivity
[3] P. Wambacq, F. Fernández, G. Gielen, W. Sansen, and A. Rodríguez-Vázquez, “Efficient Symbolic Computation of Approximated Small-signal Characteristics” IEEE Journal. Solid-State Circuits, vol. 30, pages. 327–330, Mar 1995.
[4] R. A Rutenbar, G. G. E. Gielen, and J. Roychowdhury, “Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs”, Proceedings of the IEEE, pages 640-669, march 2007.
[5] 樓禹慷, “自動辨識混合訊號電路中數位區塊之方法”, 中央大學碩士論文, June 2016
[6] https://zh.wikipedia.org/wiki/SPICE
[7] CIC 國家晶片系統設計中心, “Hspice Tutorial”
[8] C. Ebeling, “GeminiII: A Second Generation Layout Validation Tool”, Proceedings of the Conference on Computer Aided Design (ICCAD), pp.610-615, Nov 1988.
[9] C. Ebeling, and O. Zajicek, “Validating VLSI Circuit Layout by Wirelist Comparison”, Proceedings of the Conference on Computer Aided Design (ICCAD), pp. 172-173, 1993.
[10] M. Ohlrich, C. Ebeling, E. Ginting, and L. Sather, “SubGemini: Identifying Subcircuits Using a Fast Subgraph Isomorphism Algorithm”, Proceedings of Design Automation Conference, pp. 31-37, June 1993.
[11] Z. Ling, and D. Y. Y. Yun, “An Efficient Subcircuit Extraction Algorithm by Resource Management” , 2nd International Conference on ASIC, pp. 9-14, Oct 1996.
[12] L. Huang, T. Y. Jiang, J. Y. Jou, H.L. Huang, “An Efficient Logic Extraction Algorithm Using Partitioning and Circuit-Encoding,” in Proceeding International Symposium on Circuits and Systems, 2004
[13] N. P. Keng, and D. Y. Y. Yun, “A Planning /Scheduling Methodology for the Constrained Resource Problem”, Proceedings 1989 International Joint Conference on Artificial Intelligence, pp. 20-25, Aug 1989.
[14] M. Eick, “Structure and Signal Path Analysis for Analog and Digital Circuits”, Ph.D. Dissertation, Department Electrical Engineering and Information Technology., Technische Universitt München, München, Germany, 2013
[15] https://en.wikipedia.org/wiki/555_timer_IC
[16] 林慶和, “適用於類比電路區塊之解析式行為模型產生器及數位化建模技術”, 中央大學碩士論文, October 2016
[17] Y. J. Lin, M. J. Lee, Y. L. Lo, and S. Y. Kao, “Automatic Mixed-Signal Behavioral Model Generation Environment”, International Symposium on VLSI Design Automation and Test, April 2016
[18] T. Massier, “The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis”, IEEE Computer-Aid Design of Integrated Circuit and Systems, December 2008

指導教授

周景揚(Jing-Yang Jou)

審核日期

2018-1-29

推文