參考文獻 |
[1] Radu Marculescu, Umit Y. Ogras, Li-Shiuan Peh, Natalie Enright Jerger and Yatin Hoskote, "Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, 3-21, January 2009.
[2] M.-C. F. Chang, V. Roychowdhury, L. Zhang, H. Shin, and Y. Qian, "RF/wireless interconnect for inter- and intra-chip communications," Proceedings of The IEEE, vol. 89, no. 4, pp. 456-466, April 2001.
[3] B. A. Floyd, C.-M. Hung, and K. K. O, "Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters," IEEE Journal of Solid-State Circuits, vol. 37, no. 5, pp. 543-552, May 2002.
[4] K. Kimoto and T. Kikkawa, “Transmission characteristics of gaussian monocycle pulses for inter-chip wireless interconnections using integrated antennas," Japanese Journal of Applied Physics, vol. 44, no. 4B, pp. 2761-2765, April 2005.
[5] T. Kikkawa, P. K. Saha, N. Sasaki, and K. Kimoto, "Gaussian monocycle pulse transmitter using 0.18µm cmos technology with on-chip integrated antennas for inter-chip uwb communication," IEEE Journal of Solid-State Circuits, vol. 43, no. 5, pp. 1303–1312, May 2008.
[6] W. M. N. Sasaki, K. Kimoto and T. Kikkawa, "A single-chip ultra-wideband receiver silicon integrated antennas for inter-chip wireless interconnection," IEEE Journal of Solid-State Circuits, vol. 44, no. 2, pp. 382-393, February 2009.
[7] Dan Zhao, Yi Wang, Jian Li, Takamaro Kikkawa, “Design of Multi-Channel Wireless NoC to Improve On-Chip Communication Capacity”, Proceedings of the 2011 Fifth IEEE/ACM International Symposium on Networks on Chip (NoCS), pp. 177-184, July 2011.
[8] K. Kawasaki, Y. Akiyama, K. Komori, M. Uno, H. Takeuchi, T. Itagaki, Y. Hino, Y. Kawasaki, K. Ito, and A. Hajimiri, "A millimeter-wave intra-connect solution," in Digest of International Solid-State Circuits Conference, pp. 413-415, February 2010.
[9] International Technology Roadmap for Semiconductors: Semiconductor Industry 14 Association, 2006.
[10] S. B. Lee et al., "A scalable micro wireless interconnect structure for CMPs," in Proc. ACM Annu. Int. Con. Mobile Comput. Network. (Mo-biCom), pp. 217-228, 2009.
[11] D. DiTomaso et al., "iWise: Inter-router wireless scalable express chan-nels for Network-on-Chips (NoCs) architecture," in Proc. Annu. Symp. High Performance Interconnects, pp. 11-18, August 2011.
[12] S. Deb, A. Ganguly, P. Pande, D. Heo, and B. Belzer, "Wireless NOC as interconnection backbone for multicore chips: Promises and challenges," IEEE J. Emerg. Sel. Topics Circuits Syst., vol. 2, no. 2, pp. 228-239, June 2012.
[13] D. Zhao and Y. Wang, “SD-MAC: Design and Synthesis of a Hardware-efficient Collision-free QoS-aware MAC Protocol for Wireless Network-on-chip,” IEEE Transaction on Computer, vol. 57, no. 9, pp. 1230-1245, September 2008.
[14] Chifeng Wang, Wen-Hsiang Hu, Nader Bagherzadeh, “A Wireless Network-on-Chip Design for Multicore Platforms”, Proceedings of International Euromicro Conference on Parallel, Distributed and Network-Based Processing, pp. 409-416, February 2011.
[15] Amin Rezaei, Farshad Safaei, Masoud Daneshtalab, Hannu Tenhunen, “HiWA: A Hierarchical Wireless Network-on-Chip Architecture”, Proceedings of High Performance Computing & Simulation (HPCS), 2014 International Conference on IEEE, pp. 499-505, 2014.
[16] Wan-Chi Chang, Hsueh-Wen Tseng, Chin-Fu Kuo, “A Traffic-Balanced Routing Scheme for Heat Balance in 3D Networks-on-Chip”, Proceedings of SAC ′14 Proceedings of the 29th Annual ACM Symposium on Applied Computing, pp. 1437-1442, March 2014.
[17] Kun-Chih Chen,, Shu-Yen Lin, Hui-Shun Hung, An-Yeu (Andy) Wu, “Topology-Aware Adaptive Routing for Nonstationary Irregular Mesh in Throttled 3D NoC Systems”, Proceedings of IEEE Transactions on Parallel and Distributed Systems,Vol. 24, no. 10, pp. 2109-2120, October 2013.
[18] Dominic DiTomaso, Avinash Kodi, David Matolak, Savas Kaya, Soumyasanta Laha, and William Rayess, “Energy-efficient Adaptive Wireless NoCs Architecture”, Proceedings of Networks on Chip (NoCS), 2013 Seventh IEEE/ACM International Symposium on. IEEE, 2013, pp. 1-8, April 2013.
[19] Md Shahriar Shamim, Aniket Mhatre, Naseef Mansoor, Amlan Ganguly, Gill Tsouri, “Temperature-aware Wireless Network-on-Chip Architecture”, Proceedings of Green Computing Conference (IGCC), 2014 International, pp. 1-10, November 2014.
[20] S.J. Koester, G. Dehlinger, J.D. Schaub, J.O. Chu, Q.C. Ouyang, and A. Grill. Germanium-on-Insulator Photodetectors. In 2nd IEEE International Conference on Group IV Photonics, pages 171-173, 2005.
[21] Se ́bastien Le Beux, Jelena Trajkovic, Ian O ́ Connor, Gabriela Nicolescu, Guy Bois, and Pierre Paulin. “Optical Ring Network-on-Chip (ORNoC): Architecture and Design Methodology. " In Proceedings of the conference on Design, Automation and Test in Europe, DATE, pp. 1-6, March2011.
[22] M. A. Khan, A. Q. Ansari., " Quadrant-Based XYZ Dimension Order Routing Algorithm for 3-D Asymmetric Torus Networ-on-Chip," Proceedings of the in Networks and Computer Communications(ETNCC), pp. 121-124, April 2011.
[23] Masoumeh Ebrahimi, Xin Chang, Masoud Daneshtalab., " DyXYZ: Fully Adaptive Routing Algorithm for 3D NoCs," Proceedings of 2013 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, pp.499-503, March 2013.
[24] M.-C. Frank Chang, Eran Socher, Sai-Wang Tam, Jason Cong and Glenn Reinman, "RF Interconnects for Communications On-chip," Proceedings of ISPD ′08 Proceedings of the 2008 international symposium on Physical design, pp. 191-202, February 2008.
[25] Ashif Iqbal Sikder, Avinash Kodi, Matthew Kennedy, Savas Kaya and Ahmed Louri, “OWN: Optical and Wireless Network-on-Chip for Kilo-core Architectures,” 2015 IEEE 23rd Annual Symposium on High-Performance Interconnects, pp. 44-51, August 2015.
[26] A. Varga et al. ,"The OMNeT++ discrete event simulation system", In Proc. of the European Simulation Multiconference (ESM’2001), pp. 319-324, 2001.
[27] Y. Ben-Itzhak, E. Zahavi, I. Cidon, and A. Kolodny, "NoCs simulation framework for OMNeT++", in Proc. of NOCS, pp.265-266, May 2011.
[28] Jenhui Chen and Peng Dai, "Multicast Transmission with Energy-Proportional Power-Gating Scheme for Wireless Interconnects NoC", 2015 IEEE Globecom Workshops (GC Wkshps), pp.1-6, December 2011.
[29] S. Deb, et al., “Design of an Energy Efficient CMOS Compatible NoC Architecture with MillimeterWave Wireless Interconnects,” IEEE Trans. Comput., vol. 62, no. 12, pp. 2382-2396, Dec. 2013.
[30] A. Ganguly, K. Chang, S. Deb, P. P. Pande, et al., “Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems,” IEEE Trans. Comput., vol. 60, no. 10, pp. 1485-1502, Oct. 2011.
[31] V. F. Pavlidis, E. G. Friedman, “3-D Topologies for Networks-on-Chip,” IEEE Trans. VLSI Syst., vol. 15, no. 10, pp. 1081-1090, Oct. 2007.
[32] A. Shacham, K. Bergman, L. P. Carloni, “Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors,” IEEE Trans. Computer, vol. 57, no. 9, pp. 1246-1260, Sept. 2008.
[33] M. F. Chang, J. Cong, A. Kaplan, et al., “CMP Network-on-Chip Overlaid With Multi-band RF-Interconnect,” in Proc. IEEE HPCA’08, Salt Lake City, UT, pp. 191-202, Feb. 2008.
[34] H.Takagi and L. Kleinrock, “Throughput Analysis for Persistent CSMA Systems,” IEEE Trans. Commun., vol. 33, no. 7, pp. 627-638, July 1985.
[35] A. B. Kahng, B. Li, L.-S. Peh, and K. Samadi, “ORION 2.0: A Power-Area Simulator for Interconnection Networks,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. vol. 20, no. 1, pp. 191-196, Jan. 2012.
[36] H.-S. Wang, X. Zhu, L.-S. Peh, and S. Malik, “Orion: A Power- Performance Simulator for Interconnection Networks,” in Proc. IEEE/ACM MICRO’2002, Istanbul, Turkey, pp. 294-305, Nov. 2002.
[37] Peng Dai, Jenhui Chen, Yiqiang Zhao and Yen-Han Lai, “A study of a wire–wireless hybrid NoC architecture with an energy-proportional multicast scheme for energy efficiency,” in Proc. Computers & Electrical Engineering, vol. 45, no. 1, pp. 402-416, July 2015.
[38] Tavakoli E, Tabandeh M, Kaffash S, Raahemi B. “Multi-hop communications on wireless network-on-chip using optimized phased-array antennas,” Comput Electr Eng 2013, vol. 39, no. 7, pp. 2068-2085, October 2013.
[39] Yu X, Sah SP, Deb S, Pande PP, Belzer B, Deukhyoun H. “A wideband body-enabled millimeter-wave transceiver for wireless network-on-chip,” In: Proc IEEE MWSCAS’2011, Seoul, Korea, pp. 1-4, 2011.
[40] Benini L, Micheli GD. “Networks on chips: a new SoC paradigm,” Computers, vol. 35, no. 1, pp. 70-78, August 2002.
[41] Samman F, Hollstein T, Glesner M. “Adaptive and deadlock-free tree-based multicast routing for networks-on-chip,” IEEE Trans VLSI 2010, vol. 18, no. 7, pp. 1067-1080, July 2010.
[42] Samman F, Hollstein T, Glesner M. “New theory for deadlock-free multicast routing in wormhole-switched virtual-channelless networks-on-chip,” IEEE Trans Parallel Distrib Syst 2011, vol. 22, no. 4, pp. 544-557, February 2011.
[43] Ebrahimi M, Daneshtalab M, Liljeberg P, Plosila J, Flich J, Tenhunen H. “Path-based partitioning methods for 3d networks-on-chip with minimal adaptive routing,” IEEE Trans Comput 2014, vol. 63, no. 3, pp. 718-733, March 2014.
[44] Pavlidis VF, Friedman EG. “3-D topologies for networks-on-chip,” In: Proc. IEEE int’l SoC conf., Taipei, Taiwan, p. 285–288, 2006.
[45] Lee S-E, Bagherzadeh N. “A high level power model for Network-on-Chip (NoC) router,” Comput Electr Eng 2009, vol. 35, no. 6, pp. 837-845, November 2009.
[46] Boppana RV, Chalasani S, Raghavendra CS. “Resource deadlocks and performance of wormhole multicast routing algorithms,” IEEE Trans Parallel Distrib Syst, vol. 9, no. 6, pp. 535-549, August 1998.
[47] D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. P. Jouppi, M. Fiorentino, A. Davis, N. Binkert, R. G. Beausoleil, and J. H. Ahn, “Corona: System implications of emerging nanophotonic technology,” in ACM SIGARCH Computer Architecture News, IEEE Computer Society, vol. 36, no. 3, pp. 153–164, 2008.
[48] Y. Pan, P. Kumar, J. Kim, G. Memik, Y. Zhang, and A. Choudhary, “Firefly: illuminating future network-on-chip with nanophotonics,” in ACM SIGARCH Computer Architecture News, vol. 37, no. 3, pp. 429–440, 2009.
[49] G. Kurian, J. E. Miller, J. Psota, J. Eastep, J. Liu, J. Michel, L. C. Kimer- ling, and A. Agarwal, “Atac: a 1000-core cache-coherent processor with on-chip optical network,” in Proceedings of the 19th international con- ference on Parallel architectures and compilation techniques, pp. 477–488, 2010.
[50] V. Stojanovic, A. Joshi, C. Batten, Y.-J. Kwon, and K. Asanovic, “Many- core processor networks with monolithic integrated cmos photonics,” in Conference on Lasers and Electro-Optics. Optical Society of America, p. 1-2, 2009.
[51] C. Sun, C.-H. Chen, G. Kurian, L. Wei, J. Miller, A. Agarwal, L.-S. Peh, and V. Stojanovic, “Dsent-a tool connecting emerging photonics with electronics for opto-electronic networks-on-chip modeling,” in Networks on Chip (NoCS), 2012 Sixth IEEE/ACM International Symposium on. IEEE, pp. 201-210, 2012.
[52] A. Kodi and A. Louri, “A system simulation methodology of optical interconnects for high-performance computing systems,” J. Opt. Netw, vol. 6, no. 12, pp. 1282-1300, 2007. |