應用於第五代行動通訊 FR1 頻段小型基地站之連續模式與多悌氮化鎵單晶與準單晶微波積體電路功率放大器之研製

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林信潔(Hsin-Chieh Lin) 查詢紙本館藏

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電機工程學系

論文名稱

應用於第五代行動通訊 FR1 頻段小型基地站之連續模式與多悌氮化鎵單晶與準單晶微波積體電路功率放大器之研製
(Implementations on Continuous Mode and Doherty GaN MMIC and Quasi-MMIC Power Amplifier Designs for 5G NR FR1 Microcell Applications)

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摘要(中)

本篇論文之主旨係針對「應用於第五代行動通訊 FR1 頻段小型基地站之連續模式與多悌氮化鎵單晶與準單晶微波積體電路功率放大器」之設計與討論，論文利用穩懋半導體公司 (WINTM) 所提供之0.45-µm 、0.25-µm 碳化矽氮化鎵製程與砷化鎵整合式被動元件製程分別設計應用於5G NR FR1 n77、n78、n79頻段之小型基地台功率放大器。考慮到成本與未來進行更複雜電路設計的可能，除了單晶以外也採用了準單晶的組合式結構。為了能讓運作時產生的熱量充分散逸，採用了板上晶片黏著與磅線組裝，並且依據電磁模擬結果決定其組裝的磅線數量與長度。電路結構以多悌和連續模式兩種操作模式分別設計。其中一組多悌準單晶兩級功率放大器達到操作頻寬3.35 - 4.2 GHz，在連續波模式輸出飽和功率41.08 dBm，最高增益 20.3 dB，最高功率附加效率 28.2%。其中兩組J 類連續模式準單晶兩級功率放大器分別達到操作頻寬2.85 - 4.48 GHz 與2.84 - 4.47 GHz，在脈衝波模式輸出飽和功率40.3 dBm與40.0 dBm，增益 21.7 dB 與 21.6 dB，最高功率附加效率 39.3% 與 36.5%。其中一組F 類連續模式單晶兩級功率放大器達到輸出功率頻寬為3.6 - 5.4 GHz，在連續波模式輸出飽和功率41.08 dBm，最高增益 20.4 dB，最高功率附加效率 50.9%。並且對本論文所設計組裝之四組功率放大器進行實際操作下的溫度量測，經由量測得到功率放大器於連續波或脈衝波操作模式下之晶片溫度推算其故障前之平均時間，確認其在實際安裝操作下的可行性。

摘要(英)

The main purpose of this dissertation is to develop the "Implementations on Continuous Mode and Doherty GaN MMIC and Quasi-MMIC Power Amplifier Designs for 5G NR FR1 Microcell Applications". This dissertation adopted the 0.45-µm and 0.25-µm gallium nitride on silicon carbide processes and gallium arsenide integrated passive device process provided by WINTM Semiconductors to design power amplifiers for microcell base stations in the 5G NR FR1 n77, n78, and n79 bands. Considering cost and the possibility of more complex circuit designs in the future, Quasi-MMIC structures were used. To ensure effective heat dissipation during operation, chip-on-board and wire bonding assembly techniques were employed. The selection of the number and length of bonding wires was confirmed by electromagnetic simulation results. The circuit structures were designed for both Doherty and continuous modes. The Doherty Quasi-MMIC two-stage power amplifier achieved an operational bandwidth of 3.35 - 4.2 GHz, a continuous-wave output saturation power of 41.08 dBm, a maximum gain of 20.3 dB, and a maximum power-added efficiency of 28.2%. The two continuous Class J mode Quasi-MMIC two-stage power amplifiers achieved operational bandwidths of 2.85 - 4.48 GHz and 2.84 - 4.47 GHz, pulse-mode output saturation powers of 40.3 dBm and 40.0 dBm, gains of 21.7 dB and 21.6 dB, and maximum power-added efficiencies of 39.3% and 36.5%, respectively. The continuous Class F mode MMIC two-stage power amplifier achieved an output power bandwidth of 3.6 - 5.4 GHz, a continuous-wave output saturation power of 41.08 dBm, a maximum gain of 20.4 dB, and a maximum power-added efficiency of 50.9%. The dissertation also incorporates temperature measurements for the four power amplifiers that were designed and assembled. These measurements confirm the applicability of the amplifiers in both continuous-wave and pulse-mode operations, as well as the robustness of their chip temperatures and mean time to failure.

關鍵字(中)

★ 第五代行動通訊
★ 小型基地站
★ 單晶微波積體電路
★ 連續模式
★ 多悌
★ 功率放大器

關鍵字(英)

★ 5G NR
★ Microcell
★ MMIC
★ Continuous Mode
★ Doherty
★ Power Amplifier

論文目次

中文摘要 i
Abstract ii
致謝 iv
Contents vii
List of Figures ix
List of Tables xiii
Chapter 1 Introduction 1
1-1 Background and Motivation 1
1-2 Literature Review 6
1-3 Contributions 7
1-4 Dissertation Organization 8
Chapter 2 Introduction of Technologies and Assembly Design 9
2-1 Introduction of Technologies 9
2-1-1 GaN45 (NP45-11) 11
2-1-2 GaN25 (NP25-00) 11
2-1-3 GaAs IPD (IP3M-00/01) 12
2-2 Design of Assemblies and Interconnects 13
2-3 Summary 19
Chapter 3 Design of a 12.8 W Doherty Quasi-MMIC Power Amplifier 20
3-1 Introduction 20
3-2 Circuit Design 20
3-2-1 Assembly Design 20
3-2-2 Block Diagram 21
3-2-3 Coupler Circuit Design 23
3-2-4 Output Circuit Design 24
3-3 Experiment Results 30
3-3-1 Measurements 30
3-3-2 Thermal 33
3-3-3 Modulation Signal 35
3-3-4 Performance Comparison 36
3-4 Summary 37
Chapter 4 Design of 10 W 36.5 % Efficient Broadband Continuous Class-B/J Mode Quasi-MMIC Power Amplifiers 38
4-1 Introduction 38
4-2 Circuit Design 38
4-2-1 Assembly and Interconnect Design 38
4-2-2 Transistor and Bias Selection 39
4-2-3 Bias and Stability Network Design 42
4-2-4 Class-B/J output matching network 43
4-2-5 Schematics, Assemblies and 3D views 47
4-3 Experimental Results and Discussions 49
4-3-1 Chip Photographs and Assemblies 49
4-3-2 Small-Signal and Large-Signal Characterizations 50
4-3-3 Thermal 53
4-3-4 Modulation-Signal Characterizations 54
4-3-5 Discussions 57
4-4 Summary 58
Chapter 5 Design of an 8.1W 50.9% Efficient Broadband Continuous Class-F Mode MMIC Power Amplifier 60
5-1 Introduction 60
5-2 Circuit Design 60
5-2-1 Assembly Design 60
5-2-2 Transistor Selection 61
5-2-3 Bias Voltage Selection 63
5-2-4 Bias Circuit Selection 63
5-2-5 Implementation of Continuous Class-F Mode Matching Network 66
5-3 Experiment Results and Discussions 70
5-3-1 Measurements 70
5-3-2 Thermal 74
5-3-3 Modulation Signal 75
5-3-4 Performance Comparison 78
5-4 Summary 78
Chapter 6 Conclusion and Future Works 80
6-1 Conclusion 80
6-2 Future Works 82
References 83
Publication List 91

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指導教授

邱煥凱(Hwann-Kaeo Chiou)

審核日期

2024-7-25

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