閘極掘入式氮化鋁鎵/氮化鎵增強型場效電晶體之閘極蝕刻後熱退火研究

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姓名

沈沛謙(Pei-Chien Shen) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

閘極掘入式氮化鋁鎵/氮化鎵增強型場效電晶體之閘極蝕刻後熱退火研究
(The investigation of Enhancement-mode AlGaN/GaN Recessed Gate Field-Effect Transistors with Post Etching Rapid Thermal Annealing Process)

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摘要(中)

本論文研究內容主要探討閘極掘入式氮化鋁鎵/氮化鎵金絕半電容與閘極掘入式氮化鋁鎵/氮化鎵金絕半場效電晶體，一般常見的製程流程是先蒸鍍歐姆金屬後進行歐姆金屬的快速熱退火，熱退火完才進行閘極掘入。本論文所使用之製程流程是蒸鍍完歐姆金屬後先進行閘極掘入，待閘極掘入完畢後再與歐姆金屬一起進行快速熱退火，達到歐姆接觸跟閘極蝕刻後界面改善之目的。
在高蝕刻率閘極掘入式氮化鋁鎵/氮化鎵金絕半電容之特性方面，閘極掘入後經過快速熱退火處理有效改善電容的調變率、遲滯現象及頻散現象。而在閘極介電層與半導體的界面，在閘極掘入後經過快速熱退火處理也有獲得改善，且發現使用低蝕刻率之閘極掘入所製作而成的電容有最佳的界面品質。
在高蝕刻率閘極掘入式氮化鋁鎵/氮化鎵金絕半場效電晶體方面，閘極掘入後經過快速熱退火，使得元件從增強型元件轉變成空乏型元件。但在最大增益轉導值、最大汲極電流值、最小次臨界擺幅、導通電阻、元件關閉時的漏電流方面，皆是閘極掘入後經過快速熱退火之特性較佳，且由遲滯效應去估算介面缺陷密度，跟電容之電導法萃取有相似的趨勢。最後使用低蝕刻率之閘極掘入所製作而成的金絕半場效電晶體擁有最佳的元件特性 (Vth = 2.12 V、ID, max = 233.24 mA/mm、(I_on/I_off ) = 1.73  107，μmax = 143.14 cm2/Vs)。

摘要(英)

In this study, a new process flow was proposed, which is ohmic contact annealing and post etching annealing at the same time to improve the surface states after gate recess and form good ohmic contact. The enhancement mode (E-mode) GaN MIS-FETs and MIS-capacitor with recessed gate were fabricated and investigated. And the difference in device DC performances when device with proposed annealing and device with traditional ohmic annealing are compared.
In recessed-gate MIS-capacitor with high etching rate, device with proposed annealing (annealing after gate recess) shows better capacitance modulation, capacitance dispersion and lower hysteresis than the device with traditional ohmic annealing (without annealing after gate recess). The interface state density between the gate dielectric layer and the semiconductor has been effectively improved in devices with proposed annealing. In addition, it has been found that using a low etching rate to produce the recessed-gate MIS-capacitor could result in the best interface quality.
In recessed-gate MIS-FET with high etching rate for gate recess, device with proposed annealing turns into depletion-mode operation from enhancement-mode operation, but gm, max, ID, max, S.S.min, Ron, leakage current at off state are better than device with traditional annealing. The hysteresis effect in device I-V characteristics is used to estimate the interface state density, which is similar to the conductance extraction result in C-V measurements. Finally, MIS-FET with low etching rate for gate recess process emonstrates the best device characteristics, and is our laboratory′s first GaN enhancement mode device.

關鍵字(中)

★ 氮化鎵
★ 閘極掘入
★ 閘極蝕刻後熱退火

關鍵字(英)

★ GaN
★ gate recess
★ post etching annealing

論文目次

中文摘要 I
Abstract II
致謝 III
圖目錄 VI
表目錄 XI
第一章緒論 1
1.1 前言 1
1.2 氮化鎵場效電晶體及蝕刻後處理研究發展概況 3
1.2.1 增強型氮化鎵場效電晶體發展概況 3
1.2.2 蝕刻後處理研究發展概況 23
1.3 研究動機與目的 26
1.4 論文架構 26
第二章磊晶結構與元件特性模擬 27
2.1 前言 27
2.2 氮化鋁鎵/氮化鎵於矽基板之磊晶結構與分析 27
2.2.1 磊晶結構 27
2.2.2 材料分析 31
2.3 元件特性模擬 36
2.3.1 閘極蝕刻深度與臨界電壓之變化 36
2.3.2 界面缺陷對元件特性影響 37
2.4 結論 39
第三章閘極掘入式氮化鎵金絕半電容之蝕刻後快速熱退火處理之研究 40
3.1 前言 40
3.2 介電層/半導體界面缺陷種類介紹 40
3.3 閘極掘入式氮化鎵金絕半電容之製作流程 42
3.4 閘極掘入式氮化鎵金絕半電容之特性量測分析 46
3.4.1 有無蝕刻後快速熱退火處理之閘極掘入式氮化鎵金絕半電容特性 46
3.4.2 低蝕刻率之閘極掘入式金絕半電容特性 57
3.5 結論 59
第四章閘極掘入式氮化鎵金絕半場效電晶體之蝕刻後快速熱退火處理之研究 60
4.1 前言 60
4.2 閘極掘入式氮化鎵金絕半場效電晶體製作流程 60
4.3 閘極掘入式氮化鎵金絕半場效電晶體特性量測分析 61
4.3.1 有無蝕刻後快速熱退火處理之閘極掘入式氮化鎵金絕半場效電晶體特性 61
4.3.2 低蝕刻率之閘極掘入式金絕半場效電晶體特性 75
4.4 結論 81
第五章結論與未來展望 83
參考文獻 85
附錄 I Silvaco TCAD模擬參數及元件結構圖 88
附錄 II 詳細製程流程 89

參考文獻

[1] SemiconductorTODAY, “GaN to grow at 9% CAGR to over 18% of RF device market by 2020,” SemiconductorTODAY, 2014.
[2] Philip Zuk, “High-Voltage Silicon MOSFETs, GaN, and SiC: All have a place,” EDN Network, 2012.
[3] Yong Cai, Yugang Zhou, Kevin J. Chen, and Kei May Lau, “High-Performance Enhancement-Mode AlGaN/GaN HEMTs Using Fluoride-Based Plasma Treatment,” IEEE Electron Device Lett., vol. 26, no. 7, pp. 435–437, July 2005.
[4] Yong Cai, Yugang Zhou, Kei May Lau, and Kevin J. Chen, “Control of Threshold Voltage of AlGaN/GaN HEMTs by Fluoride-Based Plasma Treatment: From Depletion Mode to Enhancement Mode,” IEEE Trans. Electron Devices., vol. 53, no. 9, pp. 2207–2215, Sep. 2006.
[5] Di Song, Jie Liu, Zhiqun Cheng, Wilson C. W. Tang, Kei May Lau, and Kevin J. Chen, “Normally Off AlGaN/GaN Low-Density Drain HEMT (LDD-HEMT) With Enhanced Breakdown Voltage and Reduced Current Collapse,” IEEE Electron Device Lett., vol. 28, no. 3, pp. 189–191, March 2007.
[6] Yuhao Zhang, Min Sun, Sameer J. Joglekar, and Tomas Palacios, “High Threshold Voltage in GaN MOS-HEMTs Modulated by Fluorine Plasma and Gate Oxide,” 71st Device Research Conference, June 2013
[7] Saleem Hamady, Bilal Beydoun, Frederic Morancho, “A solution for channel electron migration in normally-off MIS-HEMT with buried fluorine ions,” 29th International Conference on Microelectronics, Dec. 2017
[8] Yasuhiro Uemoto, Masahiro Hikita, Hiroaki Ueno, Hisayoshi Matsuo, Hidetoshi Ishida, Manabu Yanagihara, Tetsuzo Ueda, Tsuyoshi Tanaka and Daisuke Ueda, “A Normally-off AlGaN/GaN Transistor with RonA =2.6mΩcm2 and BVds= 640V Using Conductivity Modulation,” 2006 International Electron Devices Meeting, Dec. 2006
[9] Liang-Yu Su, Finella Lee, and Jian Jang Huang, “Enhancement-Mode GaN-Based High-Electron Mobility Transistors on the Si Substrate With a P-Type GaN Cap Layer, “IEEE Trans. Electron Devices., vol. 61, no. 2, pp.460–464, Feb. 2014.
[10] Sarosij Adak, Sanjit Kumar Swain, Hafizur Rahaman, Chandan Kumar Sarkar, “Effect of Doping in p-GaN Gate on DC performances of AlGaN/GaN Normally-off scaled HFETs, “2017 Devices for Integrated Circuit, March 2017
[11] W.B. Lanford, T. Tanaka, Y. Otoki and I. Adesida, “Recessed-gate enhancement-mode GaN HEMT with high threshold voltage, “Electronics Letters, vol. 41, no. 7, March 2005
[12] Ye Wang, Maojun Wang, Bing Xie, Cheng P. Wen, Jinyan Wang, Yilong Hao, Wengang Wu, Kevin J. Chen, and Bo Shen, “High-Performance Normally-Off Al2O3/GaN MOSFET Using a Wet Etching-Based Gate Recess Technique, “IEEE Electron Device Lett., vol. 34, no. 11, pp.1370–1372, Nov. 2013.
[13] Ting-En Hsieh, Edward Yi Chang, Yi-Zuo Song, Yueh-Chin Lin, Huan-Chung Wang, Shin-Chien Liu, Sayeef Salahuddin, and Chenming Calvin Hu, “Gate Recessed Quasi-Normally OFF Al2O3/AlGaN/GaN MIS-HEMT With Low Threshold Voltage Hysteresis Using PEALD AlN Interfacial Passivation Layer, “IEEE Electron Device Lett., vol. 35, no. 7, pp.732–734, July 2014.
[14] Mengyuan Hua, Zhaofu Zhang, Jin Wei, Jiacheng Lei, Gaofei Tang, Kai Fu, Yong Cai, Baoshun Zhang and Kevin J. Chen, “Integration of LPCVD-SiNx Gate Dielectric with Recessed-gate E-mode GaN MIS-FETs: Toward High Performance, High Stability and Long TDDB Lifetime, “ 2016 IEEE International Electron Devices Meeting, Dec. 2016
[15] Shaofei Liu, Maojun Wang, Ming Tao, Ruiyuan Yin, Jingnan Gao, Haozhe Sun, Wei Lin, Cheng P. Wen, Jinyan Wang, Wengang Wu, Yilong Hao, Zhaofu Zhang, Kevin J. Chen, and Bo Shen, “Gate-Recessed Normally-OFF GaN MOSHEMT With Improved Channel Mobility and Dynamic Performance Using AlN/Si3N4 as Passivation and Post Gate-Recess Channel Protection Layers, “IEEE Electron Device Lett., vol. 38, no. 8, pp.1075–1078, Aug. 2017.
[16] Ki-Sik Im, Ryun-Hwi Kim, Ki-Won Kim, Dong-Seok Kim, Chun Sung Lee, Sorin Cristoloveanu, and Jung-Hee Lee, “Normally Off Single-Nanoribbon Al2O3/GaN MISFET, “IEEE Electron Device Lett., vol. 34, no. 1, pp.27–29, Jan. 2013.
[17] David F. Brown, Yan Tang, Dean Regan, Joel Wong, and Miroslav Micovic, “Self-Aligned AlGaN/GaN FinFETs, “IEEE Electron Device Lett., vol. 38, no. 10, pp.1445–1448, Oct. 2017.
[18] J. Y. Chang , H. E Hong and H. H. Yee, “Improved Characteristics of Reactive-Ion-Etching Damage for n-GaN Epitaxial Layers after Post-Etch Treatments, “The 5th Pacific Rim Conference on Lasers and Electro-Optics, Dec. 2003
[19] Wen-Kai Wang, Yu-Jen Li, Cheng-Kuo Lin, Yi-Jen Chan, Guan-Ting Chen, and Jen-Inn Chyi, “Low Damage, Cl2-Based Gate Recess Etching for 0.3-μm Gate-Length AlGaN/GaN HEMT Fabrication, “IEEE Electron Device Lett., vol. 25, no. 2, pp.52–54, Feb. 2004.
[20] L. Shen, T. Palacios, C. Poblenz, A. Corrion, A. Chakraborty, N. Fichtenbaum, S. Keller, S. P. Denbaars, J. S. Speck, and U. K. Mishra, “Unpassivated High Power Deeply Recessed GaN HEMTs With Fluorine-Plasma Surface Treatment, “IEEE Electron Device Lett., vol. 27, no. 4, pp.214–216, Apr. 2006.
[21] Tzung-Han Tsai, Min Yang, Li-Cheng Chang and Chao-Hsin Wu, “Reduction of Threshold Voltage Instability in Recessed-gate AlGaN/GaN MOSHEMTs by KOH Passivation, “2016 Compound Semiconductor Week, June 2016
[22] O. Ambacher, J. Smart, J. R. Shealy, N. G. Weimann, K. Chu, M. Murphy, W. J. Schaff, and L. F. Eastman, “Two-dimensional electron gases induced by spontaneous and piezoelectric polarization charges in N- and Ga-face AlGaN/GaN heterostructures,” Journal of Applied Physics., vol. 85, no. 6, pp. 3222–3233, Mar. 1999.
[23] D. Balaz, “Current Collapse and Device Degradation in AlGaN/GaN Heterostructure Field Effect Transistors,” University of Glasgow, 2010.
[24] E. H. Nicollian and A. Goetzberger, “The Si-SiO2 Interface - Electrical Properties as Determined by the Metal-Insulator-Silicon Conductance Technique,” Bell Syst. Tech. J, vol. 46, pp. 1055-1133, 1967.
[25] S. Huang, Q. Jiang, S. Yang, Z. Tang, and K. J. Chen, “Mechanism of PEALD-Grown AlN Passivation for AlGaN/GaN HEMTs: Compensation of Interface Traps by Polarization Charges,” IEEE Electron Device Lett., vol. 34, no. 2, pp. 193–195, Feb. 2013.
[26] Huaxing Jiang , Chak Wah Tang, and Kei May Lau, “Enhancement-Mode GaN MOS-HEMTs With Recess-Free Barrier Engineering and High-k ZrO2 Gate Dielectric, “IEEE Electron Device Lett., vol. 39, no. 3, pp.405–408, March 2018.

指導教授

辛裕明(Yue-ming Hsin)

審核日期

2018-8-6

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