應用於1Gbps車用乙太網路傳輸之 等化器與時序回復電路實現

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姓名

林祐平(You-Ping Lin) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於1Gbps車用乙太網路傳輸之等化器與時序回復電路實現
(Implementation of Equalizer and Timing Recovery Circuit for 1Gbps Automotive Ethernet Transmission)

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摘要(中)

本論文依據IEEE 802.3bp™-2016標準的車用下世代Gigabit乙太網路傳輸為模擬環境，提出接收機通道等化器以及時序迴路的演算法與電路設計。由於有線通道相較於無線通道屬於緩慢時變通道，不會有劇烈變化，因此在通道等化器上可以採用低複雜度的LMS 演算法來克服通道效應。其中通道等化器包含了前饋等化器以及決策回授等化器，前者用來消除前符碼間干擾，後者用來消除後符碼間干擾。時序迴路則採用鎖相迴路來克服兩個因素，分別是傳送端數位-類比轉換器與接收端類比-數位轉換器的時脈不匹配效應以及通道的角度偏移效應。此外，通道等化器及時序迴路因會發生交互作用而造成時序迴復電路有失敗之危機，本論文有針對此議題提出解決之道。硬體實現上先利用Xilinx ISE Design Suite撰寫，透過SMIMS VeriEnterprise Xilinx FPGA進行即時驗證電路功能，且經由Design Compiler來驗證在製程為TSMC 40nm下的電路功能，最後也使用相同製程來設計晶片。

摘要(英)

In order to develop an IEEE 802.3bp™-2016 compatible next generation gigabit Ethernet transceiver for automotive environment, the algorithms and circuits for channel equalization and timing recovery are presented in this thesis. In order to overcome the harmful inter-symbol interference (ISI), feedforward equalizer and decision feedback equalizer are employed to deal with pre-cursor and post-cursor of inter-symbol interference, respectively. Since the wired channels are slow time-variant, the low complexity Least Mean Square (LMS) algorithm can be adopted to update the coefficients of equalizer. In timing recovery, Phase-Lock Loop (PLL) will overcome two factors that are resulted from channel response and the clock mismatch between AD/DA converters, respectively. Furthermore, the phenomenon induced by the interaction of equalization and timing recovery is combated by the proposed timing recovery approach. Finally, this design is coded on Xilinx ISE Design Suite, verified on SMIMS VeriEnterprise Xilinx FPGA and Design Compiler. And then the proposed design is implemented in 40nm CMOS technology.

關鍵字(中)

★ 等化器
★ 時序回復

關鍵字(英)

★ Equalizer
★ Timing Recovery

論文目次

摘要 I
ABSTRACT II
致謝 III
目錄 IV
圖目錄 VII
表目錄 IX
第一章緒論 1
1.1 背景 1
1.2 研究動機 3
1.3 論文架構 3
第二章等化器介紹 4
2.1 濾波器架構 4
2.2 等化器種類 6
2.2.1 線性等化器 6
2.2.2 非線性等化器 8
2.3 等化器演算法 9
2.3.1 最小均根(Least Mean Square, LMS) 9
2.3.2 決策最小均根(Sign-LMS) 12
2.3.3 延遲最小均根(Delay-LMS) 13
2.3.4 可適應消除等化器(Adaptive Canceler Equalizer, ACE) 14
2.4 盲目等化器演算法 16
2.4.1定值模數演算法(Constant Modulus Algorithms, CMA) 16
2.4.2 雙模式定值模數演算法(Dual mode CMA) 18
第三章時序回復介紹 19
3.1 基本介紹 19
3.2 鎖相迴路原理 21
3.3鎖相迴路分析 24
第四章系統架構與模擬結果 26
4.1 系統架構 26
4.2 模擬環境 28
4.2.1 通道 28
4.2.2 配對器 29
4.3等化器模擬結果 30
4.3.1 可適應消除等化器模擬結果 30
4.3.2 決策回授等化器模擬結果 32
4.4鎖相迴路模擬結果 34
第五章電路架構與晶片實現 40
5.1硬體設計規格 40
5.2硬體電路介紹 41
5.2.1等化器電路 41
5.2.2 鎖相迴路電路 44
5.3設計流程 45
5.4定點數模擬分析 46
5.5模擬驗證 47
5.6晶片設計結果 49
第六章結論與未來展望 51
參考文獻 52

參考文獻

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指導教授

薛木添(Muh-Tian Shiue)

審核日期

2019-1-3

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