參考文獻 |
[1] International Roadmap for Devices and Systems (IRDS), 2016. [https://irds.ieee.org/]
[2] C. C. Wu et al., "High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme," 2010 International Electron Devices Meeting, 2010, pp. 27.1.1-27.1.4.
[3] T. Yamashita et al., "Sub-25nm FinFET with advanced fin formation and short channel effect engineering," 2011 Symposium on VLSI Technology - Digest of Technical Papers, 2011, pp. 14-15.
[4] J. A. Smith et al., "Investigation of electrically gate-all-around hexagonal nanowire FET (HexFET) architecture for 5 nm node logic and SRAM applications," 2017 47th European Solid-State Device Research Conference (ESSDERC), Leuven, 2017, pp. 188-191.
[5] S. Kim, M. Guillorn, I. Lauer, P. Oldiges, T. Hook and M. Na, "Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond," 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Rohnert Park, CA, 2015, pp. 1-3.
[6] Suk, Sung et al., "High performance 5nm radius Twin Silicon nanowire MOSFET(TSNWFET): Fabrication on bulk Si wafer, characteristics, and reliability" Technical Digest - International Electron Devices Meeting, IEDM, 2005. 717 - 720. 10.1109/IEDM.2005.1609453.
[7] J. Valasek, "Piezo-Electric and Allied Phenomena in Rochelle Salt," Physical Review, vol. 17, pp. 475, 1921.
[8] J. Müller et al., "Ferroelectricity in HfO2 enables nonvolatile data storage in 28 nm HKMG," 2012 Symposium on VLSI Technology - Digest of Technical Papers, 2012, pp. 25-26.
[9] H. Mulaosmanovic et al., "Evidence of single domain switching in hafnium oxide based FeFETs: Enabler for multi-level FeFET memory cells," 2015 IEEE International Electron Devices Meeting, 2015, pp. 26.8.1-26.8.3.
[10] S. Dünkel et al., "A FeFET based super-low-power ultra-fast embedded NVM technology for 22nm FDSOI and beyond," 2017 IEEE International Electron Devices Meeting (IEDM), 2017, pp. 19.7.1-19.7.4.
[11] S. Salahuddin and S. Datta, "Use of negative capacitance to provide voltage amplification for low power nanoscale devices," Nano Lett., vol. 8, no. 2, pp. 405–410, 2008.
[12] C. W. Yeung, A. I. Khan, A. Sarker, S. Salahuddin and C. Hu, "Low power negative capacitance FETs for future quantum-well body technology," 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2013, pp. 1-2.
[13] H. Ota, T. Ikegami, J. Hattori, K. Fukuda, S. Migita and A. Toriumi, "Fully coupled 3-D device simulation of negative capacitance FinFETs for sub 10 nm integration," 2016 IEEE International Electron Devices Meeting, 2016, pp. 12.4.1-12.4.4.
[14] M. H. Lee et al., "Physical thickness 1.x nm ferroelectric HfZrOx negative capacitance FETs," 2016 IEEE International Electron Devices Meeting, 2016, pp. 12.1.1-12.1.4.
[15] Z. Krivokapic et al., "14nm Ferroelectric FinFET technology with steep subthreshold slope for ultra low power applications," 2017 IEEE International Electron Devices Meeting, 2017, pp. 15.1.1-15.1.4.
[16] P. Sharma, J. Zhang, K. Ni and S. Datta, "Time-Resolved Measurement of Negative Capacitance," in IEEE Electron Device Letters, vol. 39, no. 2, pp. 272-275, Feb. 2018.
[17] University of Cambridge,Teaching and learning packages, [https://www.doitpoms.ac.uk/tlplib/ferroelectrics/index.php]
[18] V. P.-H. Hu, P.-C. Chiu, A. B. Sachid and C. Hu, "Negative capacitance enables FinFET and FDSOI scaling to 2 nm node," 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2017, pp. 23.1.1-23.1.4.
[19] Z. C. Yuan et al., "Switching-Speed Limitations of Ferroelectric Negative-Capacitance FETs," in IEEE Transactions on Electron Devices, vol. 63, no. 10, pp. 4046-4052, Oct. 2016.
[20] K. S. Li et al., "Sub-60mV-swing negative-capacitance FinFET without hysteresis," 2015 IEEE International Electron Devices Meeting, 2015, pp. 22.6.1-22.6.4.
[21] M. H. Lee et al., "Prospects for ferroelectric HfZrOx FETs with experimentally CET=0.98nm, SSfor=42mV/dec, SSrev=28mV/dec, switch-off <0.2V, and hysteresis-free strategies," 2015 IEEE International Electron Devices Meeting, 2015, pp. 22.5.1-22.5.4.
[22] S. Barraud et al., "Performance and design considerations for gate-all-around stacked-NanoWires FETs," 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2017, pp. 29.2.1-29.2.4.
[23] P.-C. Chiu and V. P.-H. Hu, "Analysis of Negative Capacitance UTB SOI MOSFETs considering Line-Edge Roughness and Work Function Variation," 2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM), Kobe, 2018, pp. 13-15.
[24] J. P. Duarte et al., "Compact models of negative-capacitance FinFETs: Lumped and distributed charge models," 2016 IEEE International Electron Devices Meeting (IEDM), 2016, pp. 30.5.1-30.5.4.
[25] Sanghoon Lee, Heung-Jae Cho, Younghwan Son, D. S. Lee and H. Shin, "Characterization of oxide traps leading to RTN in high-k and metal gate MOSFETs," 2009 IEEE International Electron Devices Meeting (IEDM), Baltimore, MD, 2009, pp. 1-4.
[26] T. Nagumo, K. Takeuchi, T. Hase and Y. Hayashi, "Statistical characterization of trap position, energy, amplitude and time constants by RTN measurement of multiple individual traps," 2010 International Electron Devices Meeting, San Francisco, CA, 2010, pp. 28.3.1-28.3.4.
[27] N. Tega et al., "Increasing threshold voltage variation due to random telegraph noise in FETs as gate lengths scale to 20 nm," 2009 Symposium on VLSI Technology, Honolulu, HI, 2006, pp. 50-51.
[28] Y. F. Lim et al., "Random Telegraph Signal Noise in Gate-All-Around Si-FinFET With Ultranarrow Body," in IEEE Electron Device Letters, vol. 27, no. 9, pp. 765-768, Sept. 2006.
[29] C. Hsu, C. Pan and A. Naeemi, "Performance Analysis and Enhancement of Negative Capacitance Logic Devices Based on Internally Resistive Ferroelectrics," in IEEE Electron Device Letters, vol. 39, no. 5, pp. 765-768, May 2018.
[30] S. K. Samal, S. Khandelwal, A. I. Khan, S. Salahuddin, C. Hu and S. K. Lim, "Full chip power benefits with negative capacitance FETs," 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Taipei, 2017, pp. 1-6.
[31] M. Fan, V. P. Hu, Y. Chen, P. Su and C. Chuang, "Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits," in IEEE Transactions on Electron Devices, vol. 59, no. 8, pp. 2227-2234, Aug. 2012.
[32] V. P.-H. Hu, P.-C. Chiu and Y.-C. Lu, "Impact of Work Function Variation, Line-Edge Roughness, and Ferroelectric Properties Variation on Negative Capacitance FETs," in IEEE Journal of the Electron Devices Society, vol. 7, pp. 295-302, 2019.
[33] H. Lee and P. Su, "Suppressed Fin-LER Induced Variability in Negative Capacitance FinFETs," in IEEE Electron Device Letters, vol. 38, no. 10, pp. 1492-1495, Oct. 2017.
[34] Z.-T. Lin and V. P.-H. Hu, "Performance Analysis of Gate-All-Around Negative Capacitance Stacked Nanowire and Negative Capacitance Nanosheet FETs," Extended Abstracts of the 2018 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, September 2018.
[35] Z.-T. Lin and V. P.-H. Hu, "Reduced RTN Amplitude and Single Trap induced Variation for Ferroelectric FinFET by Substrate Doping Optimization," 2019 Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan, 2019, pp. 1-2.
[36] Suman Datta, non-ECS seminar in Purdue Univ., 2015 |