Ka頻段輻射計接收機暨Ku頻段氮化鎵功率放大器之研製

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姓名

蔡智斌(Jhih-Bin Cai) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

Ka頻段輻射計接收機暨Ku頻段氮化鎵功率放大器之研製
(Design of Ka-band Radiometer Receiver and Ku-band GaN Power Amplifier)

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至系統瀏覽論文 (2025-7-20以後開放)

摘要(中)

本論文主要研究為微波及毫米波前端收發機電路中輻射計接收機及功率放大器。其中，輻射計接收機包含兩個子電路，分別為低雜訊放大器及功率偵測器。
第二章提出了一個使用台積電90 nm CMOS製程操作於Ka頻段低雜訊放大器，作為輻射計接收機之前級放大器，以提高整體系統靈敏度。為達到低雜訊且高增益特性，使用源極退化電感並且以三級疊接架構實現。電路最大增益達到14.2 dB，3 dB頻寬為32至41 GHz，在33.5 GHz有最小值雜訊指數為5 dB。晶片面積為0.9 × 0.77 mm2。
第三章提出了一個使用台積電90 nm CMOS製程操作於Ka頻段功率偵測器，作為輻射計接收機中一個子電路。為改善功率偵測器之響應度及雜訊等效功率，本次設計採用差動對架構實現。差動對架構所需差動訊號，因此於前級加入一個主動式平衡轉不平衡器。量測結果在33 GHz有最大響應度(RV)為45 kV/W與最小雜訊等效功率(NEP)為144 fW/√("Hz" )，晶片面積為0.8 × 0.75 mm2。
第四章提出了一個使用台積電90 nm CMOS製程操作於Ka頻段輻射計接收機，本章節整合了低雜訊放大器及功率偵測器。改良低雜訊放大器後，與功率偵測器整合。量測結果在34 GHz有最大響應度(RV)為4.5 MV/W與最小雜訊等效功率(NEP)為3.6 fW/√("Hz" )，晶片面積為1.54 × 0.76 mm2。
第五章提出了一個使用穩懋0.25 μm GaN製程操作於Ku頻段Doherty功率放大器，功率放大器在發射機系統中為一個關鍵電路，為改善功率放大器之回退6 dB功率增進效益(PAE)，本次設計採用Doherty架構。量測結果在14 GHz有最大功率增益為5 dB，輸出飽和功率(PSAT)為30 dBm，功率增進效益(PAE)為16%，晶片面積為1.5 × 2 mm2。
最後，於第六章提出本論文總結與未來研究方向。

摘要(英)

In this thesis, a radiometer receiver and a power amplifier in microwave and millimeter-wave front-end transceiver are presented. The radiometer receiver includes two block, low noise amplifier (LNA) and power detector.
In chapter 2, a Ka-band low noise amplifier using TSMC 90 nm process is presented as a pre-amplifier for radiometer receiver to improve the system sensitivity. To achieve low noise and high gain, inductive source degeneration and three-stage cascode architecture are used. The measured small signal gain is 14.2 dB with 3-dB bandwidth from 32 to 41 GHz, and minimum noise figure of 5 dB at 33.5 GHz. The chip size of the LNA is 0.9 × 0.77 mm2.
In chapter 3, a Ka-band power detector using TSMC 90 nm process is presented as a block for radiometer receiver. To improve the power detector responsivity (RV) and noise equivalent power (NEP), differential pair architecture is used. The active balun is used to provide the differential signal to the input of the power detector. The power detector has a measured peak responsivity of 45 kV/W and a noise equivalent power of 144 fW/√("Hz" ). The chip size of the power detector is 0.8 × 0.75 mm2.
In chapter 4, a Ka-band radiometer receiver using TSMC 90 nm process is presented. The improved LNA and the power detector are integrated in this chapter. The radiometer receiver has a measured peak responsivity of 4.5 MV/W and a noise equivalent power of 3.6 fW/√("Hz" ). The chip size of the power detector is 1.54 × 0.76 mm2.
In chapter 5, a Ku-band Doherty power amplifier using WIN 0.25 μm GaN process is presented. The power amplifier is a crucial block in the transmitter system. To improve the 6-dB power back-off efficiency, the Doherty architecture is used. The measured small signal gain is 5 dB at 14 GHz. The proposed PA achieves 30 dBm saturated output power with 16% power added efficiency (PAE) at 14 GHz. The chip size of the power amplifier is 1.5 × 2 mm2.
In chapter 6, the conclusion and future works are presented.

關鍵字(中)

★ 低雜訊放大器
★ 功率偵測器
★ 輻射計接收機
★ 功率放大器
★ 氮化鎵

關鍵字(英)

★ Low noise amplifier
★ Power detector
★ Radiometer receiver
★ Power amplifier
★ GaN
★ CMOS

論文目次

摘要 IX
Abstract X
致謝 XII
目錄 XIV
圖目錄 XVII
表目錄 XXIII
第一章緒論 1
1.1 研究動機及背景 1
1.2 相關研究發展 1
1.3 論文貢獻 3
1.4 論文架構 3
第二章 Ka頻段三級低雜訊放大器 4
2.1 簡介 4
2.1.1 重要參數介紹 4
2.2 製程簡介 6
2.2.1 台積電 90 nm CMOS 製程 6
2.3 電路設計與分析 7
2.4 電路模擬與量測 16
2.5 電路除錯分析 21
2.6 總結 26
第三章 Ka頻段功率偵測器 28
3.1 簡介 28
3.1.1 功率偵測器介紹 28
3.1.2 重要參數介紹 29
3.2 製程簡介 30
3.2.1 台積電 90 nm CMOS 製程 30
3.3 電路設計與分析 30
3.4 電路模擬與量測 38
3.5 電路除錯分析 46
3.6 總結 49
第四章 Ka頻段輻射計接收機 51
4.1 簡介 51
4.2 製程簡介 51
4.2.1. 台積電 90 nm CMOS 製程 51
4.3 電路設計與分析 52
4.4 電路模擬與量測 57
4.5 電路除錯分析 66
4.6 總結 68
第五章 Ku頻段Doherty功率放大器 70
5.1 簡介 70
5.2 製程簡介 70
5.2.1. 穩懋0.25 μm GaN 製程 70
5.3 電路設計與分析 71
5.4 電路模擬與量測 80
5.5 總結 88
第六章結論 90
參考文獻 91

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指導教授

張鴻埜(Hong-Yeh Chang)

審核日期

2020-7-21

推文