參考文獻 |
[1] J. Scheible and J. Lienig “Automation of Analog IC Layout Challenges and Solutions” Proc, International Symposium on Physical Design, pp.33-40, 2015
[2] H. Chi, H. Tseng, C. J. Liu and H. Chen, "Performance-preserved analog routing methodology via wire load reduction," 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), July, 2018, pp. 482-487
[3] A. B. Kahng, P. Sharma and R. O. Topaloglu, "Exploiting STI stress for performance," 2007 IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2007
[4] B. Xu et al., "MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper," 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
[5] N. H. Ricardo Martins, Nuno Lourenc¸o, Analog Integrated Circuit Design Automation Placement, Routing and Parasitic Extraction Techniques. Springer Publishing Company, Inc., 2017.
[6] Q. Ma, L. Xiao, Y. Tam, and E. F. Y. Young, “Simultaneous handling of symmetry, common centroid, and general placement constraints,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 1, pp. 85–95, Jan 2011.
[7] M. P. H. Lin, Y. W. Chang, and C. M. Hung, “Recent research development and new challenges in analog layout synthesis,” in Asia and South Pacific Design Automation Conference, Jan 2016, pp. 617–622.
[8] F. Balasa and K. Lampaert, “Module placement for analog layout using the sequence-pair representation,” in Proc. DAC, 1999, pp. 274-279.
[9] J.-M. Lin, G.-M. Wu, Y.-W. Chang, and J.-H. Chuang, “Placement with symmetry constraints for analog layout design using TCG-S,” in Proc. ASP-DAC, 2005, pp. 1135-1138.
[10] P.-H. Lin and S.-C. Lin, “Analog placement based on novel symmetry-island formulation,” in Proc. DAC, 2007, pp.465-470.
[11] C.-W. Lin, C.-C. Lu, J.-M. Lin, and S.-J. Chang, “Routability-driven placement algorithm for analog integrated circuits,” in International Symposium on Physical Design, Mar 2012, pp. 71–78.
[12]Chris Chu and Yiu-Chung Wong, “FLUTE: Fast lookup table based rectilinear Steiner minimal tree algorithm for VLSI design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 1, pp. 70–83, Jan. 2008.
[13] Hongxia Zhou, Chiu-Wing Sham, and Hailong Yao. 2017. Revisiting routability-driven placement for analog and mixed-signal circuits. ACM Transactions on Design Automation of Electronic Systems (TODAES) 23, 2, 172017.
[14] H.-C. Ou, K.-H. Tseng, J.-Y. Liu, I.-P. Wu, and Y.-W. Chang, “Layout-dependent-effects-aware analytical analog placement,” in Proc. DAC,2015.
[15] H.-C. Chang, "Routing with Cell Movement in Analog Layout", Master Thesis, NCTU, 2020
[16] H.-Y. Chi, Z.-J. Lin, C.-H. Hung, C.-N. J. Liu, H.-M. Chen, "Achieving Routing Integrity in Analog Layout Migration via Cartesian Detection Lines", in Proc. ICCAD, Nov. 2019.
[17] C. Du, Y. Cai, X. Hong, “A Novel Analog Routing Algorithm with Constraints of Variable Wire Widths,” in Proc International Conference on Communications, Circuits and Systems, pages 2459-2463, 2006
[18] A. Patyal, P. Pan, A. K. A, H. Chen and W. Chen, "Exploring Multiple Analog Placements with Partial-Monotonic Current Paths and Symmetry Constraints using PCP-SP," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Feb 2020
[19] 黃弘一, “Ch03-Analog Layout Consideration,” 混合訊號積體電路佈局與分析課程講義, Jan.2001.
[20] Yi-Peng Weng, Hung-Ming Chen, Tung-Chieh Chen, Po-Cheng Pan, Chien-Hung Chen, and Wei-Zen Chen, “Fast analog layout prototyping for nanometer design migration,” Proc. International Conference Computer -Aided Design, pp. 517–522, 2011.
[21] J. Xue et al., “A framework for layout-dependent STI stress analysis and stress-aware circuit optimization,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 3, pp. 498–511, Mar. 2012.
[22] X. Li, Z. Ye, Y. Tan, and Y. Wang, “A two-dimensional analysis method on STI-aware layout-dependent stress effect,” IEEE Transactions on Electron Devices, vol. 59, no.11, pp. 2964 - 2972, 2012
[23] Hongxia Zhou, Chiu-Wing Sham, and Hailong Yao. 2017. Revisiting routability-driven placement for analog and mixed-signal circuits. ACM Transactions on Design Automation of Electronic Systems (TODAES) 23, 2, 172017.
[24] R. Martins, R. P´ovoa, N. Lourenc¸o, and N. Horta, “Current-flow and current-density-aware multi-objective optimization of analog ic placement,” Integration, the VLSI Journal, vol. 55, pp. 295–306, Sept 2016.
[25] Mentor Graphic® Caliber®, http://www.mentor.com
[26]Y.-Ch. Chang, Y.-W. Chang, G.-M. Wu, and Sh.-W. Wu, “B*-Trees: A new representation for non-slicing floorplans,” Proc. Design Automation Conference, pp. 458-463, 2000.
[27] P.-H. Lin and S.-C. Lin, “Analog Placement Based on Novel Symmetry-Island
Formulation,” Proc. of DAC, pp. 465–470, Jun. 2007.
[28] X. Tang, R. Tian, and D. F. Wong, “Fast Evaluation of sequence pair in block placement by longest common subsequence computation,” in Proc. Design Automation Test Europe, pp. 106–111, 2000. |