使用二次諧波注入增強技術之毫米波除六注入鎖定除頻器與正交鎖相迴路之研製

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：45

、訪客IP：3.136.19.41

姓名

劉正賢(CHANG-HSHEN LIU) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

使用二次諧波注入增強技術之毫米波除六注入鎖定除頻器與正交鎖相迴路之研製
(Millimeter Wave Divide-by-6 Injection-Locked Frequency Divider with Second Harmonic Enhancement and Orthogonal Phase-Locked Loops)

相關論文

★ 微波及毫米波切換器及四相位壓控振盪器整合除三除頻器之研製	★ 微波低相位雜訊壓控振盪器之研製
★ 高線性度低功率金氧半場效電晶體射頻混波器應用於無線通訊系統	★ 砷化鎵高速電子遷移率之電晶體微波/毫米波放大器設計
★ 微波及毫米波行進波切換器之研製	★ 寬頻低功耗金氧半場效電晶體射頻環狀電阻性混頻器
★ 微波與毫米波相位陣列收發積體電路之研製	★ 24 GHz汽車防撞雷達收發積體電路之研製
★ 低功耗低相位雜訊差動及四相位單晶微波積體電路壓控振盪器之研究	★ 高功率高效率放大器與振盪器研製
★ 微波與毫米波寬頻主動式降頻器	★ 微波及毫米波注入式除頻器與振盪器暨射頻前端應用
★ 寬頻主動式半循環器與平衡器研製	★ 雙閘極元件模型與微波及毫米波分佈式寬頻放大器之研製
★ 銻化物異質接面場效電晶體之研製及其微波切換器應用	★ 微波毫米波寬頻振盪器與鎖相迴路之研製

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

至系統瀏覽論文 (2027-8-1以後開放)

摘要(中)

本論文主要探討注入鎖定除頻器與四相位鎖相迴路之研究，在現今的毫米波頻段的收發機系統與雷達中，皆需要一個穩定且乾淨的振盪源，而本地振盪源通常以鎖相迴路來達成。因注入鎖定除頻器易操作在高頻，使注入鎖定除頻器普遍應用在毫米波頻段的鎖相迴路中的第一級除頻器，需要低功耗、高鎖定頻寬之特性，本論文主要針對高鎖定頻寬進行設計分析。
第二章介紹應用於鎖相迴路之K頻段四相位壓控振盪器，本次設計使用TSMC 0.18-μm¬ CMOS 的製程來完成此章節的電路設計。此章節會先簡介變壓器回授及耦合之理論，接著會對兩者架構模擬不同的耦合係數及匝數比對相位雜訊及輸出功率之影響。此外此章節探討數種耦合方式並對其耦合強度進行分析，並說明其優缺點，在其中挑選自我注入耦合來達成四相位壓控振盪器。此次電路設計成功實現出K頻段輸出訊號，分別使用變壓器回授及變壓器回授與耦合兩種電路設計並比較其電路性能，其中變壓器回授頻率可調範圍為22.94到24.5 GHz(1.56 GHz)，輸出功率大於-15.6 dBm。相位雜訊最好的值為-102 dBc/Hz控制電壓在1.5 V時，相位誤差及振幅誤差最大為5.5度及1.8 dB。變壓器回授及耦合之頻率可調範圍為21.61到22.71 GHz(1.1 GHz)，輸出功率大於-15.9 dBm。相位雜訊最好的值為-94.6 dBc/Hz控制電壓在1.3 V時，相位誤差及振幅誤差最大為8.2度及2.5 dB。
第三章使用電流再利用技術來完成 V 頻段注入鎖定除頻器之設計，此章節電路架構利用兩級注入鎖定除頻器來完成除六除頻器之設計，最後使用 TSMC 90 nm GUTM CMOS 來完成此電路設計。由參考文獻中得知二次注入之增強鎖定頻寬技術。在此章節比較有二次注入兩種及無二次注入電路架構共有三種，從相關文獻進一步修正除頻器理論計算結果，提升鎖定頻寬理論計算結果與實驗結果的吻合性。驗證電路架構能有效的增強鎖定頻寬，並比較其鎖定頻寬。最後在電路設計裡也使用諧波增強技術來進一步加強除頻器之鎖定頻寬。量測時，注入訊號功率為 0 dBm，鎖定頻寬為 59.3 到 65.7 GHz，鎖定範圍為 6.4 GHz 相當於 7%的比例頻寬，電路的直流消耗為 14.3 mW。與模擬相比注入訊號功率為 0 dBm，鎖定頻寬為 55.8 到 64.2 GHz，鎖定範圍為 8.4 GHz 相當於 14 %的比例頻寬。模擬與量測中心頻率頻偏2.5 GHz鎖定頻寬減少2 GHz，如何除錯將在本章說明。
第四章為K頻段四相位鎖相迴路，電路使用TSMC0.18 μm互補式金屬氧化物半導體製程設計並實現，鎖相迴路包含變壓器回授四相位壓控振盪器、相位頻率偵測器、電荷幫浦、迴路濾波器、兩級注入鎖定除頻、兩級電流模式除頻器及三級單相位時序除頻器。在量測時分別對振盪器與迴路個別量測，量測時振盪器的頻率可調範圍增加 1 GHz振盪器增益增加1.8 GHz/V，導致迴路在無法鎖定會有迴路振盪的問題，會在本章節說明如何調整量測電壓使迴路鎖定，並探討迴路振盪的原因。模擬鎖定頻率範圍為22.02 GHz至23.49 GHz。量測鎖定範圍為22.189 GHz至24.02 GHz，相位雜訊最好的頻率為22.2- GHz在1 MHz頻率偏移時為-99 dBc/Hz，抖動為1 ps，相位雜訊最差的頻率為24 GHz在1 MHz頻率偏移時為-81.2 dBc/Hz，抖動為1.2 ps。抑制量小於-31.2¬¬ dBc，直流總功耗為90 mW

摘要(英)

This paper mainly discusses the research on the injection-locked frequency divider and the four-phase phase-locked loop. In today′s millimeter-wave transceiver systems and radars, a stable oscillator source is required, and the local oscillator source is usually a Phase-locked loop. In addition, the injection-locked frequency dividers (ILFD) are also employed in the millimeter-wave PLL due to their high speed and low DC power consumption, and the ILFD can be adopted as the first-stage frequency divider in the PLL.
The sond chapter introduces the K-band Quadrature voltage-controlled oscillator applied to the phase-locked loop. This design uses the TSMC 0.18 μm CMOS process to complete the circuit design of this chapter. This chapter first introduces the theory of transformer-feedback and transformer-coupled, and then simulate the effects of different coupling coefficients and turns ratio on phase noise and output power for the two architectures. In addition, this chapter discusses several coupling methods, analyzes their coupling strength, and explains their advantages and disadvantages. Among them, self-injection coupling is selected to achieve a four-phase VCO. This circuit design successfully realized the K-band output signal. Two circuits, transformer feedback, and transformer feedback and coupling were used to design and compare performance. The frequency of the transformer-feedback is 22.94 GHz when the control voltage is 0 V. The output power is 22.94 GHz. When the control voltage is 1.8 V, the frequency is 24.5 GHz, the output power is -15.6 dBm, and the frequency adjustable range is 1.5 GHz. The best value for phase noise is -102 dBc at 1.5 V control voltage. The maximum phase error and amplitude error are 5.5 degrees and 1.8 dB, and the output power of transformer feedback and coupling is -15.2 dBm when the control voltage is 0 V and the frequency is 21.61 GHz; when the control voltage is 1.8 V, the output power is - 22.71 GHz. 15.9 dBm, frequency adjustable to 1.1 GHz. The best value for phase noise is -94.6 dBc at the control voltage of 1.3 V. Phase error and amplitude difference up to 8.2 degrees and 2.5 dB
In Chapter 3, a current-reused technique is employed in a V-band ILFD. The circuit design of the presented ILFD is first presented with some theoretical calculations and simulations. Furthermore, a double-injection technique is also employed in the ILFD circuit design to enhance the locking range, and the ILFD is realized using a TSMC 90-nm CMOS VI process. As compared with prior art, the proposed ILFD features wide locking range and low DC power. With an input power of 0 dBm, the measured locking range is 59.3 to 65.7 GHz, locking range is 6.4 GHz, which corresponds to a proportional bandwidth of 7 %, and the DC consumption of the circuit is 14.3 mW. Compared to analog, the injected signal power is 0 dBm, the bandwidth is 55.8 to 64.2 GHz, and the lock range is 8.4 GHz, which corresponds to a proportional bandwidth of 14%. Simulate and measure the center frequency offset 2.5 GHz and lock the bandwidth by 2 GHz. How to debug will be explained in this chapter.
In Chapter 4,K-band Quadrature phase-locked loop. The PLL is using TSMC 0.18 μm CMOS process design and implementation. The building blocks of the PLL include a QVCO, a phase-frequency detector, a charge pump, a loop filter, two-stage ILFD and two-stage common-mode logic dividers and three-stage true single phase clocking dividers. In the VCO, the tunning range is increased by 2 GHz, and the gain of the oscillator is increased by 1.8 GHz/V, which causes the phenomenon of loop oscillation. How to debug will be explained in this chapter. The locking range from 22.02 GHz to 23.49 GHz, measurement locking range from 22.189 GHz to 24.02 GHz, phase noise -90 dBc/Hz at 1 MHz frequency offset, total DC power consumption 90 mW

關鍵字(中)

★ 鎖相迴路
★ 正交鎖相迴路
★ 注入鎖定除頻器
★ 二次諧波注入增強
★ 毫米波頻段

關鍵字(英)

★ Phase-Locked Loops
★ Orthogonal Phase-Locked Loops
★ ILFD
★ Second Harmonic Enhancement
★ Millimeter Wave

論文目次

摘要 i
目錄 v
圖目錄 viii
表目錄 xvi
第一章緒論 1
1.1 研究動機及背景 1
1.2 相關研究發展 1
1.3 論文貢獻 4
1.4 論文架構 5
第二章 K頻段變壓器回授及耦合四相位壓控振盪器 6
2.1 簡介 6
2.2 電路設計及分析 7
2.2.1差動之壓控振盪器設計 7
2.2.2.1 變壓器回授壓控振盪器之設計 7
2.2.2.2 變壓器耦合壓控振盪器[44] 15
2.2.3 四相位耦合 25
2.2.4 四相位壓控振盪器 29
2.2.4.1變壓器回授 29
2.2.4.2變壓器回授與變壓器耦合 32
2.3 電路實現及實驗結果與討論 35
2.3.1 四相位變壓器回授壓控振盪量測結果 38
2.3.2 四相位變壓器回授及耦合壓控振盪量測結果 41
2.3.3 四相位變壓器回授壓控振盪量測除錯 44
2.4 結論 49
第三章使用電流再利用及諧波增強鎖定頻寬之V頻段注入鎖定除六除頻器 51
3.1 架構簡介 51
3.2 二次注入[53] 51
3.3注入式除三除頻器理論計算分析 54
3.3.1.1傳統電流再利用除三除頻器鎖定頻寬分析 57
3.3.1.2二次注入式除三除頻器 70
3.4 使用電流再利用及諧波增強鎖定頻寬之 V 頻段注入鎖定除六除頻器 72
3.4.1電路設計 72
3.5.2實驗結果與討論 78
3.3 總結 90
第四章 K頻段正交鎖相迴路 93
4.1 簡介 93
4.2 電路設計及分析 94
4.2.1. 四相位壓控振盪器 95
4.2.2. 除頻器 97
4.2.3. 相位頻率偵測器與電荷幫浦 102
4.3.1. 迴路濾波器的設計與挑選[48] 105
4.3.2. 整合鎖相迴路系統模擬與分析 108
4.3 電路實現與結果討論 111
4.3.1 鎖相迴路之量測 113
4.3.2鎖相迴路量測除錯 119
4.4 總結 136
第五章結論 138
參考文獻 139

參考文獻

[1] B. Afshar and A. M. Niknejad, “A robust 24 mW 60 GHz receiver in 90 nm standard CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2008, pp. 182–183.
[2] K. Kang, F. Lin, D.-D. Pham, J. Brinkhoff, C.-H. Heng, Y. X. Guo, and X. Yuan, “A 60- GHz OOK receiver with an on-chip antenna in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 9, pp. 1720–1731, Sep. 2010.
[3] K. Okada et al., “A 60- GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver for IEEE 802.15.3c,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2988–3004, Dec. 2011.
[4] V. Jain, B. Javid, and P. Heydari, “A BiCMOS dual-band millimeterwave frequency synthesizer for automotive radars,” IEEE J. Solid-StateCircuits, vol. 44, no. 8, pp. 2100–2113, Aug. 2009.
[5] A. Arbabian, S. Callender, S. Kang, B. Afshar, J.-C. Chien, and A. Niknejad, “A 90 GHz hybrid switching pulsed-transmitter for medical imaging,” IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2667–2681, Dec. 2010.2113, Aug. 2009.
[6] D. Murphy, Q. J. Gu, Y.-C. Wu, H.-Y. Jian, Z. Xu, A. Tang, F. Wang, and M.-C. F. Chang, “A low phase noise, wideband and compact CMOS PLL for use in a heterodyne 802.15.3c transceiver,” IEEE J. Solid-State Circuits, vol. 46, no. 7, pp.1606-1617, Jul. 2011.
[7] A. Arbabian, S. Kang, S. Callender, J.-C. Chien, B. Afshar, and A. Niknejad, “A 94 GHz mm-wave to baseband pulsed-radar for imaging and gesture recognition,” IEEE Int. Symp. on VLSI Design, Automation and Test, Jun. 2012, pp. 56-57.
[8] A. Arbabian, S. Callender, S. Kang, M. Rangwala, and A. Niknejad, “A 94 GHz mm-wave-to-baseband pulsed-radar transceiver with applications in imaging and gesture recognition,” IEEE J. Solid-State Circuits, vol. 48, no. 4, pp. 1055–1071, Apr. 2013.
[9] M.-W. Li, P.-C. Wang, T.-H. Huang, and H.-R. Chuang, “Low-voltage, wide-locking-range, millimeter-wave divide-by-5 injection-locked frequency divider,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 3, pp. 679-685, Mar. 2012.
[10] F. Behbahani, Y. Kishigami, J. Leete, and A. A. Abidi, “CMOS mixers and polyphase filters for large image rejection,” IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 873–887, Jun. 2001.
[11] A. Natarajan, A. Komijani, X. Guan, A. Babakhani, and A. Hajimiri, “A 77-GHz phased-array transceiver with on-chip antennas in silicon: Transmitter and local LO-path phase shifting,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2807–2819, Dec. 2006.
[12] P. Andreani and X. Wang, “On the phase-noise and phase-error performances of multiphase LC CMOS VCOs,” IEEE Journal o f Solid-State Circuits, vol. 39, no. 11, pp. 1883-1893, Nov. 2004.
[13] N. C. Kuo, J. C. Chien, and A. M. Niknejad, “Design and analysis on bidirectionally and passively coupled QVCO with nonlinear coupler,” IEEE Trans Microw. Theory Tech., vol. 63, no. 4, pp. 1130-1141, Apr. 2015.
[14] T. Xi, S. Guo, P. Gui, D. Huang, Y. Fan, and M. Morgan, “Low phase-noise 54-GHz transformer-coupled quadrature VCO and 76-/90- GHz VCOs in 65-nm CMOS,” IEEE IEEE Trans Microw. Theory Tech., vol. 64, no. 7, pp. 2091-2103, Jul. 2016.
[15] X. Yi, C. C. Boon, H. Liu, J. F. Lin and W. M. Lim, "A 57.9-to-68.3 GHz 24.6 mW Frequency Synthesizer With In-Phase Injection-Coupled QVCO in 65 nm CMOS Technology," IEEE J. Solid-State Circuits, vol. 49, no. 2, pp. 347-359, Feb. 2014.
[16] H.-R. Kim, C.-Y. Cha, S.-M. Oh, M.-S. Yang, and S.-G. Lee, “A very low-power quadrature VCO with back-gate coupling,” IEEE J. Solid-State Circuits, vol. 39, no. 6, pp. 952–955, Jun. 2004.
[17] 詹駿清，毫米波注入鎖定振盪器及鎖頻迴路之研究，國立中央大學電機工程研究所碩士論文，民國 105 年。
[18] I.-S. Shen, C.-F. Jou, “A X -Band Capacitor-Coupled QVCO Using Sinusoidal Current Bias Technique,” IEEE Trans Microw. Theory Tech., vol.60, no.2, pp.318-328, Feb. 2012.
[19] P. -Y. Wang, G. -Y. Su, Y. -C. Chang, D. -C. Chang and S. S. H. Hsu, "A Transformer-Based Current-Reuse QVCO With an FoM Up to −200.5 dBc/Hz," IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 65, no. 6, pp. 749-753, Jun. 2018.
[20] H.-Y. Chang, C.-H. Lin, Y.-C. Liu, Y.-L. Yeh, K. Chen, S.-H. Wu, “65-nm CMOS Dual-Gate Device for Ka-Band Broadband Low-Noise Amplifier and High-Accuracy Quadrature Voltage-Controlled Oscillator,” IEEE Trans Microw. Theory Tech., vol.61, no.6, pp.2402-2413, Jun. 2013.
[21] 邱垣達，低功耗相位雜訊差動及四相位單晶微波積體電路壓控振盪器之研究。國立中央大學電機工程研究所碩士論文，民國100年。
[22] Q. Jiang and Q. Pan, "Analysis and Design of Tuning-Less mm-Wave Injection-Locked Frequency Dividers With Wide Locking Range Using 8th-Order Transformer-Based Resonator in 40 nm CMOS," IEEE J. Solid-State Circuits, vol. 39, no. 10, pp. 1–1, Mar. 2022.
[23] L. Zhang, A. Ameri, Y.-A. Li, N.-C. Kuo, M. Anwar, A.-M. Niknejad, “A 37.5-45. l GHz Superharmonic-Coupled QVCO with Tunable Phase Accuracy in 28nm Bulk CMOS,” IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers, pp.223-226, Nov. 2018.
[24] C. Li, L. Wu, W. Che and Q. Xue, "Phase Shift Techniques for Improving Varactor-Less QVCO Based on Rotated-Phase-Tuning," IEEE Trans. Circuits Syst. II: Exp. Briefs., vol. 69, no. 2, pp. 279-283, Feb. 2022.
[25] J. Zhu, Q. Jiang, H. Mosalam, C. Zhan and Q. Pan, "A 19–48.3 GHz 6th-Order Transformer-Based Injection-Locked Frequency Divider With 87.1% Locking Range in 40-nm CMOS," IEEE Trans. Circuits Syst. II:Exp. Briefs., vol. 68, no. 9, pp. 3053-3057, Sept. 2021.
[26] Q. Jiang and Q. Pan, "Tuning-Less Injection-Locked Frequency Dividers with Wide Locking Range Utilizing 8th-Order Transformer-Based Resonator," in IEEE Radio Frequency Integrated Circuits Symposium, 2021, pp. 159-162.
[27] H. Nam and J. Park, "A W-Band Divide-by-Three Injection-Locked Frequency Divider With Injection Current Boosting Utilizing Inductive Feedback in 65-nm CMOS," IEEE Microw. Wireless Compon. Lett., vol. 30, no. 5, pp. 516-519, May. 2020.
[28] Y.-W. Chen, T.-N. Luo, H. Cruz, and Y.-J.-E. Chen, “A W-band harmonically enhanced CMOS divide-by-three frequency divider,” IEEE Microw. Wireless Compon. Lett., vol. 24, no. 4, pp. 257–259, Apr. 2014.
[29] S. -L. Jang, G. -Z. Li and W. -C. Lai, "Wide-Locking Range RLC-Tank Balanced-Injection Divide-by-5 Injection-Locked Frequency Dividers Based on Harmonic Mixing," IEEE Trans Microw. Theory Tech., vol. 68, no. 3, pp. 894-903, Mar. 2020.
[30] 林品安，使用諧波增強高除是注入鎖定除頻器與四相位考畢子壓控振盪器之研製，國立中央大學電機工程研究所碩士論文，民國 110 年。
[31] 葉瀚濃，使用注入鎖定技術之 W 頻段除三除頻器與 V 頻段除六除頻器及 Q 頻段鎖頻迴路，國立中央大學電機工程研究所碩士論文，民國 107 年。
[32] 李昇洺，V 及 D 頻段高除數注入鎖定除頻器與四相位鎖頻迴路之研製，國立中央大學電機工程研究所碩士論文，民國 106 年。
[33] S. -L. Jang, H. -W. Lai and J. -Y. Sung, "Current-Reused Divide-by-16 Injection-Locked Frequency Divider," IEEE Microw. Wireless Compon. Lett., vol. 32, no. 5, pp. 426-429, May 2022.
[34] D. Turker et al., "A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2018, pp. 378-380.
[35] Y. Chen, L. Praamsma, N. Ivanisevic and D. M. W. Leenaerts, "A 40GHz PLL with −92.5dBc/Hz in-band phase noise and 104 fs-RMS-jitter," in proc. IEEE RFIC Symp., 2017, pp. 31-32.
[36] D. -G. Lee and P. P. Mercier, "A Sub-mW 2.4-GHz Active-Mixer-Adopted Sub-Sampling PLL Achieving an FoM of −256 dB," IEEE J. Solid-State Circuits, vol. 55, no. 6, pp. 1542-1552, Jun. 2020.
[37] J. -H. Seol, K. Choo, D. Blaauw, D. Sylvester and T. Jang, "Reference Oversampling PLL Achieving −256-dB FoM and −78-dBc Reference Spur," IEEE J. Solid-State Circuits, vol. 56, no. 10, pp. 2993-3007, Oct. 2021.
[38] D. Liao, R. Wang and F. F. Dai, "A low-noise inductor-less fractional-N sub-sampling PLL with multi-ring oscillator," in proc. IEEE RFIC Symp., 2017, pp. 108-111.
[39] A. Tharayil Narayanan et al., "A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB," IEEE J. Solid-State Circuits, vol. 51, no. 7, pp. 1630-1640, Jul. 2016.
[40] N. Markulic et al., "A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation," IEEE J. Solid-State Circuits, vol. 51, no. 12, pp. 3078-3092, Dec. 2016.
[41] T. -H. Tsai, R. -B. Sheen, S. -Y. Hsu, C. -H. Chang and R. B. Staszewski, "A 55.9-fs Integrated Jitter (100 kHz–100 MHz) Hybrid LC-Tank PLL in 5-nm FinFET Using Programmable Phase Realignment and Dynamic Coarse Tuning," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, vol. 4, pp. 230-233, 2021.
[42] W. El-Halwagy, A. Nag, P. Hisayasu, F. Aryanfar, P. Mousavi and M. Hossain, "A 28-GHz Quadrature Fractional-N Frequency Synthesizer for 5G Transceivers With Less Than 100-fs Jitter Based on Cascaded PLL Architecture," IEEE Trans Microw. Theory Tech., vol. 65, no. 2, pp. 396-413, Feb. 2017.
[43] T. -H. Tsai, R. -B. Sheen, S. -Y. Hsu, C. -H. Chang and R. B. Staszewski, "A 55.9-fs Integrated Jitter (100 kHz–100 MHz) Hybrid LC-Tank PLL in 5-nm FinFET Using Programmable Phase Realignment and Dynamic Coarse Tuning," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, vol. 4, pp. 230-233, 2021.
[44] K. Kwok and H. C. Luong, "Ultra-low-Voltage high-performance CMOS VCOs using transformer feedback," IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 652-660, Mar. 2005.
[45] Y. Chao, H. C. Luong and Z. Hong, "Analysis and Design of a 14.1-mW 50/100-GHz Transformer-Based PLL With Embedded Phase Shifter in 65-nm CMOS," IEEE Trans Microw. Theory Tech., vol. 63, no. 4, pp. 1193-1201, Apr. 2015.
[46] S.-J. Yun, S.-B. Shin, H.-C. Choi, S.-G. Lee, “A 1mW Current-Reuse CMOS Differential LC-VCO with Low Phase Noise,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, vol.1, pp.540-616, Feb. 2005.
[47] X. Yi, Z. Liang, G. Feng, C. C. Boon and F. Meng, "A 93.4-to-104.8 GHz 57 mW fractional-N cascaded sub-sampling PLL with true in-phase injection-coupled QVCO in 65 nm CMOS," in IEEE Radio Frequency Integrated Circuits Symposium, 2016, pp.122-125.
[48] Xuqiang Zheng, Fangxu Lv, Lei Zhou, Danyu Wu, Jin Wu, Chun Zhang, Woogeun Rhee and Xinyu Liu, “Frequency-Domain Modeling and Analysis of Injection-Locked Oscillators,” IEEE J. Solid-State Circuits, vol. 55, no. 6, pp.1651-1664, June. 2020.
[49] B. Razavi, RF Microelectronics, Prentice Hall, 1998.
[50] 高曜煌，射頻鎖相迴路 IC 設計，第二章，滄海書局，民國 94 年。
[51] 劉深淵、楊清淵，鎖相迴路，滄海書局，民國 100 年。
[52] 葉彥良，應用於微波及毫米波鎖相迴路之金氧半場效電晶體注入鎖定振盪器研究，國立中央大學電機工程研究所博士論文，民國 102 年。
[53] M. Abdulaziz, T. Forsberg, M. Törmänen, H. Sjöland, “A 10-mW mm-Wave Phase-Locked Loop With Improved Lock Time in 28-nm FD-SOI CMOS” IEEE Trans Microw. Theory Tech., vol.67, pp1588-1600, Apr. 2019.

指導教授

張鴻埜(Hong-Yeh Chang)

審核日期

2022-9-27

推文