具有通道熱電子注入編程能力的40nm 4kb 1T OTP陣列的設計和實現

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葉宥鋐(YOU-HONG YE) 查詢紙本館藏

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電機工程學系

論文名稱

具有通道熱電子注入編程能力的40nm 4kb 1T OTP陣列的設計和實現
(Design and Implementation of a 40nm 4kb 1T OTP Array with Channel Hot Electron Injection Programming Scheme)

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至系統瀏覽論文 (2027-10-21以後開放)

摘要(中)

隨著電子裝置記憶體容量需求增加，應用於高容量密度記憶體、低功耗、高安全性晶片需求大增，一次性可編程 (OTP) 存儲器變得越來越重要，防止存儲資料不被竄改，提供安全的密鑰存儲，相對於一般光罩式唯讀記憶體 (Mask ROM) 做比較，有更大彈性上使用，可在晶片製造後做代碼更改，有效降低除錯及更新的時間，操作速度夠快，可以直接執行代碼，無需將代碼複製到片上隨機存取記憶體 (RAM) 來執行，縮短啟動時間，使用電荷儲存 (charge storage) 操作機制，相對於反熔絲 (Anti-fuse OTP)、電子熔絲 (efuse OTP) 有較低操作電壓與面積小，低功率消耗的優勢。

本論文中分四個部分分別為解碼器、記憶體陣列、感測放大器與邏輯判斷電路，解碼器在不同操作條件下選定陣列中的位址，給予操作電壓值，確保未選到位址接地不影響編程中的元件，感測放大器採用電流感測器放大器模式進行讀取，能讀取小電流且很大感測裕度，更準確的讀取資料。

本研究設計容量為4kb的OTP記憶體陣列，在編程上有快的操作速度(1μs)與較低的編程電壓(1.8V)，單位元面積僅需0.1452μm2，面積小的之優勢。透過不同編程電壓，來達到多位元存儲，來增加記憶體容量，在讀取時可以達到很低位元錯誤率為1.76%，此記憶體陣列能在攝氏125度下烘烤740小時後仍能操作。

摘要(英)

As demand of memory capacity for increase in electronic devices, demand of highly-dense memory, low-power, and highly-secured chips also increases. One-Time Programming (OTP) memory becomes more and more important. To prevent stored data from being hacked, a secure -key storage is necessity. In comparison with the Mask ROM, One-Time Programming (OTP) memory has more flexibility. It can make code changes after the chip has been manufactured, effectively reducing time for debugging and updating. Hence, the operation speed is faster. It also eliminates the need to duplication of codes for on-chip random access memory (RAM), which reduces startup time. To support this functionality, a charge storage operating mechanism is used by users to program the OTP cell. In comparison with the anti-fuse (OTP) and electronic fuse (efuse OTP), our single-transistor charged-based one-time Programming (OTP) memory has the advantages of lower operating voltage, smaller area, and lower power consumption.
The OTP MACRO is divided into four parts: decoder, memory array, sense amplifier and logic control circuit. The decoder selects an address in the array under different operating conditions. It also applies the operating voltages to ensure that the unselected cells area not affect by the operation voltage under the selected one. The sense amplifier uses the current sensing mode for readout the information stored in the 1T OTP cell, which can read a small current amount with a large sensing margin so as to read more accurately.
This work designs an OTP memory array with the capacity of 4-k cells, which shows advantages of fast operation speed (1s) and low programming voltage (1.8V) in programming. Another benefit of this OTP memory array is smaller cell-size. The unit area is only 0.1452μm2 per cell. Furthermore, to increase memory capacity aggressively, 3-bits-per-cell storage is achieved through different incremental programming voltages. This array also achieves a low bit error rate of 1.76% when random-access is performed. As a result, reliabilities are also evaluated, the memory array can keep information after baked in 740 hours at 125 Celsius.

關鍵字(中)

★ 一次編程記憶體
★ 多位元存儲
★ 單一電晶體單元
★ 記憶體陣列

關鍵字(英)

★ One-time programming memory
★ multi-bit storage
★ 1T unit-cell
★ memory array

論文目次

摘要 I
Abstract II
致謝 IV
圖目錄 VII
表目錄 IX
第一章導論 1
1.1 背景 1
1.2 研究動機 3
1.3 論文架構 4
第二章不同OTP操作機制 5
2.1 簡介 5
2.2 不同OTP操作機制說明 5
2.3 OTP存儲編程電壓、面積、可靠度問題 7
2.6 實驗設計 7
第三章分析與設計鐵4kb 1T OTP 陣列設計 14
3.1 簡介 14
3.2 單位記憶胞(unit-cell)結構 14
3.3 不同nMOSFET, pMOSFET臨界電壓條件 15
3.4 操作條件 15
3.5 通道熱電子注入(Channel Hot electron injection) 15
3.6 Fowler-Nordheim穿隧(F-N tunneling) 16
3.7 4kb 1T-OTP陣列架構 16
3.8 解碼器設計 16
3.9 電流感測放大器 17
3.10 多次感測判斷電路與參考電阻值設計 17
第四章 4kb 1T-OTP 陣列晶片量測結果 32
4.1 簡介 32
4.2 記憶體編程操作機制 32
4.3 記憶體單元讀取時Shmoo與編程後出現位元錯誤率 33
4.4 記憶體元件抗擾性分析 34
4.5 資料高溫存儲能力測試 34
第五章結論 49
參考文獻 54

參考文獻

[1]J. Raszka, M. Advani, V. Tiwari, L. Varisco, N. D. Hacobian, A. Mittal, M. Han, A. Shirdel, and A. Shubat, "Embedded flash memory for security applications in a 0.13 μm CMOS logic process," IEEE ISSCC. Dig. Tech. Papers, 2004, vol. 1, pp. 46–512.
[2]J. Rosenberg, "Embedded flash on a CMOS logic process enables secure hardware encryption for deep submicron designs," Non-Volatile Memory Technol. Symp., 2005, pp. 19–21.
[3]H. K. Cha, I. Yun, J. Kim, B. C. So, K. Chun, I. Nam, and K. Lee, "A 32-KB standard CMOS antifuse one-time programming ROM embedded in a 16-bit microcontroller," IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 2115–2124, 2006.
[4]J. Peng, G. Rosendale, M. Fliesler, D. Fong, J.Wang, C. Ng, Z. S. Liu, and H. Luan, "A novel embedded OTP NVM using standard foundry CMOS logic technology," 21st IEEE NVSMW, 2006, pp. 24–26.
[5]V. Srinivasan, G. J. Serrano, J. Gray, and P. Hasler, "A precision CMOS amplifier using floating-gate transistors for offset cancellation," IEEE J. Solid-State Circuits, vol. 42, no. 2, pp. 280–291, 2007.
[6]W. C. Wang, C. C. Chuang, C. W. Chang, E. R. Hsieh, H. W. Chen, and S. S. Chung, "A Novel Complementary Architecture of One-time-programming Memory and Its Applications as Physical Unclonable Function (PUF) and One-time Password,"2020 IEEE International Electron Devices Meeting (IEDM), 2020, pp. 31.6.1-31.6.4
[7]C. Huang, H. Lin and C. -Y. Wu, "High-voltage tolerant circuit design for fully CMOS compatible multiple-time programming memories," 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014, pp. 1949-1952
[8]Eiji Sakagami and Kiyomi Naruke, "Nonvolatile Semiconductor Memory Device having Memory cell Transistor Provided with Offset Region Acting as a Charge Carrier injection Region," U.S. Patent 5,838,041, Oct. 2, 1996. Nov 17, 1998.
[9]Y. Zhang, Z. He, M. Wan, J. Liu, H. Gu, and X. Zou, "A SC PUF Standard Cell Used for Key Generation and Anti-Invasive-Attack Protection," IEEE Transactions on Information Forensics and Security, vol. 16, pp. 3958-3973, 2021.
[10]E. R. Hsieh, H. W. Wang, C. H. Liu;Steve S. Chung, T. P. Chen, S.A. Huang, T. J. Chen, and Osbert Cheng, "Embedded PUF on 14nm HKMG FinFET Platform: A Novel 2-bit-per-cell OTP-based Memory Feasible for IoT Secuirty Solution in 5G Era," 2019 Symposium on VLSI Technology, 2019, pp. T118-T119.
[11]W. C. Wang, C. C. Chuang, C. W. Chang, E. R. Hsieh, H. W. Chen, and S. S. Chung, "A Novel Complementary Architecture of One-time-programming Memory and Its Applications as Physical Unclonable Function (PUF) and One-time Password," 2020 IEEE International Electron Devices Meeting (IEDM), 2020, pp. 31.6.1-31.6.4.
[12]J. Im, B. Ang, S. Tumakha, and S. Paak, "Characterization of Silicided Polysilicon Fuse Implemented in 65nm Logic CMOS Technology," 2006 7th Annual Non-Volatile Memory Technology Symposium, 2006, pp. 55-57.
[13]Gang Liu, Rommel Relos, Bohumil Janik, Robert Davis, Tracy Myers, Derryl Allman, Jeff Hall, Steven Vandeweghe, Santosh Menon, and Ed Flanigan, "Polysilicon Fuse Electrical Voiding Mechanism AP/DFM: Advanced Patterning / Design for Manufacturability," 2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), 2020, pp. 1-4.
[14]Chunyan E. Tian, Dan Moy, Chuck Le, and Brian Messenger, Chandrasekharan Kothandaraman, John Safran, S. Wu, N. Robson, and Subramanian S. Iyer, "Reliability Investigation of NiPtSi Electrical Fuse With Different Programming Mechanisms," in IEEE Transactions on Device and Materials Reliability, vol. 8, no. 3, pp. 536-542, Sept. 2008.
[15]Yanjun Ma, Edwin Kan, Non-logic Devices in Logic Processes, Springer International, New York, 2007.
[16]J. Lienig and G. Jerke, "Electromigration-aware physical design of integrated circuits," 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design, 2005, pp. 77-82.
[17]Hsiao, Woan Yun, Chin Yu Mei, Wen Chao Shen, Y. D. Chih, Ya-Chin King, and C. J. Lin, "A New 28nm HKMG CMOS Logic OTP Cell," The Japan Society of Applied Physics, pp. 564-565, Sep. 2013.
[18]Sarvesh H. Kulkarni, Umaira Ikram, Kedar Bhatt, Yu-Lin Chao, Yao-Feng Chang, Ian Jenkins, Venkatesh Murari, David Thambithurai, Mohammad Hasan, Jiabo Li, Leif R. Paulson, Bernhard Sell, Uddalak Bhattacharya, and Ying Zhang, "A 5-V-Program 1-V-Sense Anti-Fuse Technology Featuring On-Demand Sense and Integrated Power Delivery in a 22-nm Ultra Low Power FinFET Process," IEEE Solid-State Circuits Letters, vol. 4, pp. 2-5, 2021.
[19]S.-K. Sung, S.-H. Lee, B. Choi, J. Lee, J.-D. Choe, E. Cho, Y. Ahn;D. Choi, C.-H. Lee, D. Kim, Y.-S. Lee, S. Kim, D. Park, and B.-I. Ryu, "SONOS-Type FinFET Device Using P+ Poly-Si Gate and High-k Blocking Dielectric Integrated on Cell Array and GSL/SSL for Multi-Gigabit NAND Flash Memory," Symposium on VLSI Technology, 2006. Digest of Technical Papers., 2006, pp. 86-87.
[20]Yi-Hung Tsai, Hsin-Ming, Chen;Hsin-Yi Chiu, Hung-Sheng Shih, Han-Chao Lai, Ya-Chin King, and Chrong Jung Lin, "45nm Gateless Anti-Fuse Cell with CMOS Fully Compatible Process," IEEE International Electron Devices Meeting, 2007, pp. 95-98.
[21]I. V. Ermakov, A. Y. Losevskoy, A. V. Nuykin, N. A. Shelepin, and A. S. Kravtsov, "Design and Study of a 65 Kb AntiFuse OTP ROM in a Standard 0.18 um CMOS Process," 2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus), 2020, pp. 112-115.
[22]Kuei-Sheng Wu, Chang-Chien Wong, Sinclair Chi, Ching-Hsiang Tseng, Purple Huang, Devon Huang, and Titan Su, "The improvement of electrical programming fuse with salicide-block dielectric film in 40nm CMOS Technology," 2010 IEEE International Interconnect Technology Conference, 2010, pp. 1-3.
[23]Guangyan Zhao, Yong Zhao, and W. -T. K. Chien, "Reliability investigations on the programming currents of 28nm metal e-Fuse," 2017 China Semiconductor Technology International Conference (CSTIC), 2017, pp. 1-3.
[24]S. -H. Song, J. Kim and C. H. Kim, "Program/erase speed, endurance, retention, and disturbance characteristics of single-poly embedded flash cells," 2013 IEEE International Reliability Physics Symposium (IRPS), 2013, pp. MY.4.1-MY.4.6.
[25]Takashi Kono, Takashi Ito, Tamaki Tsuruda, Takayuki Nishiyama, Tsutomu Nagasawa, Tomoya Ogawa, Yoshiyuki Kawashima, Hideto Hidaka, and Tadaaki Yamauchi, "40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for data," 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2013, pp. 212-213.
[26]H. Shanmuganathan and A. Mahendran, "Current Trend of IoT Market and its Security Threats," 2021 International Conference on Innovative Computing, Intelligent Communication and Smart Electrical Systems (ICSES), 2021, pp. 1-9.
[27]O. Gasparri, B. Aleksandar, P. del Croce, and A. Baschirotto, "A Low-Dropout Regulator for One Time Programming (OTP) Memories in Automotive Applications," 2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2021, pp. 1-4.
[28]M. C. Lee, R. Barsatan and M. Chan, "OTP Memory for Low Cost Passive RFID Tags," 2007 IEEE Conference on Electron Devices and Solid-State Circuits, 2007, pp. 633-636.
[29]N. D. Phan, I. J. Chang, and J. -W. Lee, "A 2-Kb One-Time Programming Memory for UHF Passive RFID Tag IC in a Standard 0.18 /spl mu/m CMOS Process," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 7, pp. 1810-1822, July 2013.
[30]P. Pavan, R. Bez, P. Olivo, and E. Zanoni, "Flash memory cells-an overview," IEEE, vol. 85, no. 8, pp. 1248-1271, Aug. 1997.
[31]T. Na, B. Song, J. P. Kim, S. H. Kang, and S. -O. Jung, "Offset-Canceling Current-Sampling Sense Amplifier for Resistive Nonvolatile Memory in 65 nm CMOS," IEEE Journal of Solid-State Circuits, vol. 52, no. 2, pp. 496-504, Feb. 2017.
[32]Z. Chen, S. H. Kulkarni, V. E. Dorgan, U. Bhattacharya, and K. Zhang, "A 0.9um2 1T1R bit cell in 14nm SoC process for metal-fuse OTP array with hierarchical bitline, bit level redundancy, and power gating," 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 2016, pp. 1-2.
[33]S. Chung, W. -K. Fang, J. Lin, W. -H. Yu, and J. Y. Hsiao, "32Kb Innovative fuse (I-Fuse) array in 22nm FD-SOI with 0.9V/1.4mA program voltage/current and 0.744um2 cell," 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2017, pp. 1-2.
[34]E. R. Hsieh, C. W. Chang, C. C. Chuang, H. W. Chen, and S. S. Chung, "The Demonstration of Gate Dielectric-fuse 4kb OTP Memory Feasible for Embedded Applications in High-k Metal-gate CMOS Generations and Beyond," 2019 Symposium on VLSI Circuits, 2019, pp. C208-C209.
[35]Martina Arosio, Chiara Boffino, Sergio Morini, Dirk Priefert, Oezguer Albayrak, Viktor Boguszewicz, and Andrea Baschirotto, "An ESD-Protected, One-Time Programming Memory Front-End Circuit for High-Voltage, Silicon-on-Insulator Technology," IEEE Transactions on Electron Devices, vol. 68, no. 6, pp. 2848-2854, June 2021.

指導教授

謝易叡張孟凡(Eray Hsieh、Meng-Fan Chang)

審核日期

2022-10-25

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