摘要(英) |
With the advancement of technology ushering in Industry 4.0, automation systems for monitoring and controlling physical equipment such as machinery and robots are facilitated through algorithms. In recent years, industrial control products such as AC servo motor controllers, industrial automation inverters, and power regulators for renewable energy require isolation devices to prevent hazardous voltage or current, thereby ensuring the safety of personnel and adjacent electronic equipment in industrial settings.
The paper implements the design of the receiver circuit applied to the optically coupled isolation system. The receiver system architecture is mainly divided into two parts, including an analog low-pass filter used to attenuate the high-frequency quantization noise of the transmission-side delta-sigma modulator. The internal circuit mainly consists of a third-order Butterworth low-pass filter, a clock data recovery circuit to generate the filter input clock and data signals. The internal circuits include a phase detector, a charge pump, a loop filter, and a voltage-controlled oscillator. Matlab simulation is used to design the transmission-side delta-sigma modulator (SDM) to generate 1-bit digital signals, and the signal-to-noise distortion ratio is 85.74dB as the input signal for the subsequent receiver. The filter circuit architecture adopts a switched-capacitor filter to achieve higher linearity, realizing the demand for the analog signal ENOB of greater than 12 bits in the receiver. For the clock data recovery circuit, the sampling frequency (20.48 MHz) is the target frequency, and a relatively low-speed Hogge linear phase detector is used for the jittery loop application. The loop filter uses a filter with amplified capacitors for a dual-path charge pump to reduce chip area. The voltage-controlled oscillator uses a five-stage current-steering inverter to generate delayed and oscillating signals.
The circuit adopts TSMC 0.18μm CMOS 1P6M process, with a chip area of approximately 1.0542×0.969695 mm2. The power supply voltage is 1.8V, and the overall circuit power consumption is 6.01 mW. The circuit bandwidth is 40 kHz, oversampling ratio (OSR) is 256,sampling frequency is 20.48 MHz. The signal-to-noise ratio (SNR) is 79.97 dB, total harmonic distortion (THD) is -83.56 dB, signal-to-noise and distortion ratio (SNDR) is 78.4 dB, and effective number of bits (ENOB) is 12.92 bits. |
參考文獻 |
[1] " TLP7820/7920 Data Sheet." Toshiba https://toshiba.semicon-storage.com/ info/docget.jsp?did=68559
[2] Fandrich C L. An on-chip transformer-based digital isolator system. Master′s thesis. The University of Tennessee, Knoxville, USA, 2013
[3] Johns, David A., and Ken Martin. Analog integrated circuit design. John Wiley & Sons, 2008.
[4] C.H. Su, “Circuit Implementation of Sigma-Delta Modulators,” Electrical Engineering, National Central University, 2007
[5] Schaumann, Rolf, Haiqiao Xiao, and Van Valkenburg Mac. Design of analog filters 2nd Edition. Oxford University Press, Inc., 2009.
[6] 林群育 , and 蘇朝琴 . 應用於鎖相迴路之高解析度相位頻率偵測法 . Diss. 2010.
[7] Bozomitu, Radu Gabriel, Neculai Cojan, and Gabriel Bonteanu. "A VLSI implementation of the 4 th order elliptic fully differential IIR switched-capacitor low-pass filter in CMOS technology." 2013 IEEE 19th International Symposium for Design and Technology in Electronic Packaging (SIITME). IEEE, 2013.
[8] Lee, K-L., and R. G. Mayer. "Low-distortion switched-capacitor filter design techniques." IEEE Journal of Solid-State Circuits 20.6 (1985): 1103-1113.
[9] B. Razavi, “Design of Analog CMOS Integrated Circuits,” Mcgraw-Hill, Second Edition, 2005
[10] 徐靜瑩 , and 林進燈 . 應用於生醫訊號之可重組三角積分調變器設計 . Diss. 2007.
[11] Choksi, Ojas, and L. Richard Carley. "Analysis of switched-capacitor common-mode feedback circuit." IEEE Transactions on Circuits and Systems II: Analog and digital signal processing 50.12 (2003): 906-917.
[12] Xu, Weize, and Eby G. Friedman. "Clock feedthrough in CMOS analog transmission gate switches." 15th Annual IEEE International ASIC/SOC Conference. IEEE, 2002.
[13] Spilka, Ronald, et al. "Generation of non-overlapping clock signals without using a feedback loop." 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE, 2012
[14] 劉深淵劉深淵, 楊清淵楊清淵, 鎖相迴路鎖相迴路, 滄海書局滄海書局,2006.
[15] Breier, Jakub, Shivam Bhasin, and Wei He. "An electromagnetic fault injection sensor using Hogge phase-detector." 2017 18th International Symposium on Quality Electronic Design (ISQED). IEEE, 2017.
[16] Das, Keshab, et al. "Comparison and Performance Analysis of Ring Oscillators and Current-Starved VCO in 180-nm CMOS Technology." 2020 International Symposium on Devices, Circuits and Systems (ISDCS). IEEE, 2020.
[17] Shekhar, Chandra, and Shafi Qureshi. "Design and analysis of current starved vco targeting scl 180 nm cmos process." 2018 IEEE International Symposium on Smart Electronic Systems (iSES)(Formerly iNiS). IEEE, 2018.
[18] 潘皇承潘皇承, and 洪浩喬洪浩喬. 一個應用於一個應用於 32~ 96KHz SPDIF/AES 訊號之時脈回復器電路的訊號之時脈回復器電路的設計設計. Diss. 2007.
[19] Huang, Jhin-fang, Jiun-yu Wen, and Yen-jung Lin. "Chip design of a 10-MHz switched capacitor low-pass filter for wireless application." 2014 Sixth International Conference on Wireless Communications and Signal Processing (WCSP). IEEE, 2014.
[20]Xu, Yang, et al. "A 0.6 mW 31MHz 4 th-order low-pass filter with+ 29dBm IIP3 using self-coupled source follower based biquads in 0.18 μm CMOS." 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits). IEEE, 2016.
[21] De Matteis, Marcello, et al. "A 63-dB DR 22.5-MHz 21.5-dBm IIP3 fourth-order FLFB analog filter." IEEE Journal of Solid-State Circuits 52.7 (2017): 1977-1986.
[22] Payandehnia, Pedram, et al. "A 0.49–13.3 MHz tunable fourth-order LPF with complex poles achieving 28.7 dBm OIP3." IEEE Transactions on Circuits and Systems I: Regular Papers 65.8 (2018): 2353-2364.
[23] Xu, Yang, et al. "A 77-dB-DR 0.65-mW 20-MHz 5th-order coupled source followers based low-pass filter." IEEE Journal of Solid-State Circuits 55.10 (2020): 2810-2818.
[24] Liu, Jialin, and David J. Allstot. "A Chopper-Stabilized Switched-Capacitor Front-End for Peripheral Nervous System Recording." IEEE Transactions on Circuits and Systems I: Regular Papers (2023). |