應用於光耦合隔離系統之發送端雜訊整形 類比轉數位轉換器

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陳琮元(Tsung-Yuan Chen) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於光耦合隔離系統之發送端雜訊整形類比轉數位轉換器
(A Design of Noise-Shaping ADC for Optical Coupling Isolation Applications)

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摘要(中)

隨著科技的發展現在正處於第四次工業革命，即工業4.0。主要著重於互聯性、自動化、機械學習和實時數據等方面。透過智慧技術、演算法和控制機械等實體設備為自動化監控和分析技術帶來革新。在近年來的工業控制產品，如交流伺服馬達控制器，工業自動化逆變器，用於再生能源的功率調節器，都需要更高的效率與精度。在工業設備中，精確測量來自物理傳感器的信號是控制系統的關鍵部分，從測量方面來看，不僅需要最大的精度且還需要確保安全性與可靠性，工業控制系統通常在危險的電壓下運行，因而廣泛需要隔離器來保護人員和相鄰的電子設備。本電路以高精準度、低功耗為目標對隔離器中的類比數位轉換器進行設計。
本論文實現應用於光耦合隔離系統之發送端類比數位轉換器，對於應用分為三角積分類比數位轉換器(Sigma-Delta ADC)與雜訊整形連續近似類比數位轉換器(Noise-Shaping Successive Approximation ADC,NS-SAR ADC)兩種類比數位轉換器，三角積分類比數位轉換器主要由三角積分調變器(Sigma-Delta Modulator, SDM)與數位降頻率波器組成，而雜訊整形連續近似類比數位轉換器以三角積分調變器轉換技術為基礎，其特性為在轉換過程中使用雜訊整形(Noise-Shaping)技術，以提高轉換精準度並降低功耗。
本電路採用台積電0.18μm CMOS 1P6M製程，晶片面積分別約佔0.556 mm2與1.291 mm2，電源供應電壓分別為1.8V與1.2V，整體電路功耗分別為4.58 mW與317 μW，電路頻寬分別為40 kHz與200 kHz，電路採樣頻率分別為20.48 MHz與3.2 MHz。都以開關電容架構下實現解析度為12 位元。

摘要(英)

With the development of technology, we are currently in the midst of the Fourth Industrial Revolution, known as Industry 4.0. It primarily focuses on aspects such as interconnectivity, automation, machine learning, and real-time data. Innovations in automation monitoring and analysis technologies are brought about through smart technologies, algorithms, and control mechanisms for physical equipment. In recent years, industrial control products such as AC servo motor controllers, industrial automation inverters, and power regulators for renewable energy require higher efficiency and precision. In industrial equipment, precise measurement from physical sensors is a crucial part of control systems. From a measurement perspective, not only the maximum accuracy is required, but also safety and reliability must be ensured. Industrial control systems typically operate under hazardous voltages, necessitating the widespread use of isolators to protect personnel and adjacent electronic equipment. This circuit aims to design analog-to-digital converters in isolators with high precision and low power consumption.
This paper implements analog-to-digital converters (ADCs) for use in optically coupled isolation systems at the transmitter end. For applications, it is divided into two types of ADCs: Sigma-Delta ADCs and Noise-Shaping Successive Approximation ADCs (NS-SAR ADCs). Sigma-Delta ADCs are mainly composed of Sigma-Delta modulators (SDMs) and digital decimation filters, while NS-SAR ADCs are based on Sigma-Delta modulation technology. Their characteristic lies in the use of noise-shaping techniques during the conversion process to improve conversion accuracy and reduce power consumption.
This circuit is implemented using TSMC′s 0.18μm CMOS 1P6M process, with chip areas approximately 0.556 mm2 and 1.291 mm2 respectively. The power supply voltages are 1.8V and 1.2V, with overall circuit power consumption of 4.58 mW and 317 μW respectively. The circuit bandwidths are 40 kHz and 200 kHz, and the circuit sampling frequencies are 20.48 MHz and 3.2 MHz respectively. A 12-bit resolution is achieved using a switched capacitor architecture.

關鍵字(中)

★ 類比轉數位轉換器
★ 連續近似類比數位轉換器
★ 雜訊整形
★ 浮動逆變放大器

關鍵字(英)

論文目次

第一章緒論. 1
1.1 背景 1
1.2 研究動機 2
1.3 論文貢獻 4
第二章三角積分調變器原理概論. 5
2.1 奈奎斯特與超取樣類比數位轉換器. 5
2.2 量化誤差 7
2.3 超取樣與雜訊整形技術 9
2.3.1 超取樣技術 9
2.3.2 雜訊整形. 11
2.4 一階三角積分調變器 13
2.5 二階三角積分調變器 14
2.6 高階三角積分調變器 15
第三章連續近似類比數位轉換器概論 17
3.1 連續近似類比數位轉換器基本架構 17
3.2 數位類比轉換器能量耗損分析. 19
3.2.1 取樣保持階段能量耗損分析 19
3.2.2 電荷重新分佈階段能量耗損分析 21
第四章類比數位轉換器設計與模擬. 25
4.1 三角積分調變器. 25
4.1.1 三角積分調變器規格訂製 25
4.1.2 三角積分調變器系統設計 25
4.1.3 電路系統非理想效應考量 27
4.1.4 電路設計. 33
4.1.5 佈局前模擬結果. 41
4.2 雜訊整形連續近似類比數位轉換器 45
4.2.1 雜訊整形連續近似類比數位轉換器規格訂製. 45
4.2.2 雜訊整形連續近似類比數位轉換器系統設計. 46
4.2.3 電路設計. 48
4.2.4 佈局前模擬結果. 60
第五章佈局考量與量測 64
5.1 三角積分調變器. 64
5.1.1 佈局平面圖 64
5.1.2 佈局後模擬結果. 65
5.1.3 量測規劃. 67
5.1.4 量測結果. 69
5.2 雜訊整形連續近似類比數位轉換器 71
5.2.1 佈局平面圖 71
5.1.2 佈局後模擬結果. 73
5.1.3 量測規劃. 75
第六章結論與未來展望 76
6.1 文獻比較. 76
6.1.1 三角積分調變器. 76
6.1.2 雜訊整形連續近似類比數位轉換器 76
6.2 未來展望. 77
參考文獻 78

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指導教授

薛木添

審核日期

2024-3-22

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