基於閾值電壓電性擾動所實現之高速亂數產生率的40-nm 4T-SRAM真亂數產生器記憶體矩陣晶片

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姓名

吳奕陞(Yi-Sheng Wu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

基於閾值電壓電性擾動所實現之高速亂數產生率的40-nm 4T-SRAM真亂數產生器記憶體矩陣晶片
(Implementation of High-speed TRNGs Composed of 40-nm Loadless 4T-SRAM Memory-array Based on the Vth Electrical Variability)

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至系統瀏覽論文 (2027-10-24以後開放)

摘要(中)

在資安技術中，真亂數產生器 ( TRNG ) 是非常重要的硬體關鍵部位之一，其主要功能是產生隨機排列的 0 與 1 字串，產生方式是經由物理現象所產生的隨機電性雜訊，將這些雜訊透過電路的方式讀取出 0 與 1 的結果，而因為這些物理現象都具有不可預測的特性，因此產生出來的隨機數列也具有完美的隨機特性，進而達到真亂數的效果。
本論文所設計的容量為 2kb 的 loadless 4T-SRAM 矩陣，其單位元件面積為 1.3975μm2，並且在一次讀寫後能一次產生出 32 bits 的隨機字串，因為在讀寫的過程，( Bitline, BL ) 會因為路徑上的 nMOS 閾值電壓值不同，因此造成讀取出的電壓會有差異，而由
於閾值電壓是因為製程時所出現的物理差異，無法被計算出影響的電壓高低，所以讀取出的電壓差值也存在著隨機特性，再透過電路的分析便可以獲得隨機的字串輸出。
而本論文所設計的 loadless 4T-SRAM 在經過電性的量測與數據分析後，其操作的輸入電壓只需 0.5 V 至 0.7 V，並且操作時間在 6 ns 附近就能產生出亂數的效果，在透過統計學的方式對輸出的字串進行 Hamming Distance、Hamming Weight 與 Autocorrelation 的分析後，透過 Hamming Distance 分析中可以發現每一個輸出的字元所發生翻轉的機
率都接近 50 %，而經由 Hamming Weight 與 Autocorrelation 的分析後，可以確定在長時間的讀取後仍能輸出穩定且不具備重複性的亂數結果，並且最後的輸出結果在常溫以及高溫的情況下都能通過 NIST test 的 15 項驗證，因此本論文提出的設計實現高效率、低功耗的目標，並且晶片在常溫以及高溫的環境中，都能穩定的輸出隨機的亂數，因此以閾值電壓值差異做為 TRNG 的 entropy 是在現今製程技術持續微縮的環境中，是非常具
有潛力的。

摘要(英)

In information security technology, the True Random Number Generator (TRNG) plays a significant role in hardware devices. Its main function is to generate random 0 and 1 strings.
The entropy of TRNG is generated by physic phenomena, and the results of 0 and 1 are read out by the noises via the circuit. Since these physic phenomena have unpredictable
characteristics, the generated random number sequence also has perfect randomness , which achieves true random numbers.
The loadless 4T-SRAM array with capacity of 2 kb designed in this thesis has unit-cell area of 1.3975 μm2 and can generate a random string of 32 bits simultaneously after one read and write. During read and write process, Bitline (BL) will be fluctuated due to Vth variation of different nMOS devices, so the readout voltage will also be different.
The loadless 4T-SRAM array is designed in this thesis. After electrical measurement and data analysis, the input voltage for the operation only needs 0.5 V to 0.7 V, and the operating time is around 6 ns to produce random numbers. For characteristics of Hamming Distance, Hamming Weight, and Autocorrelation, it can be found that each output bit shows the flipping probability which is very close to 50%. Through Hamming Weight and Autocorrelation analysis, we can determine that the results of stable and non-reproducible random numbers can be read out. Moreover, our final output results successfully passed all of the NIST test at both 25°C and 75°C. In conclusion, the design proposed in this thesis achieves goals of high efficiency, low power consumption and prefect randomness.

關鍵字(中)

★ 真亂數產生器
★ 靜態隨機存取記憶體
★ 記憶體矩陣
★ 記憶體單元

關鍵字(英)

★ True Random Number Generator
★ SRAM
★ Loadless 4T-SRAM
★ memory cell
★ memory array

論文目次

目錄
摘要 .............................................. I
Abstract ......................................... II
致謝 .............................................. III
圖目錄..............................................VI
表目錄............................................. VIII
第 1 章導論 .............................. 1
1.1 背景................................... 1
1.2 研究動機............................... 2
1.3 論文架構................................ 3
第 2 章 The unit cell of Loadless 4T-SRAM TRNG array.... 4
2.1 TRNG Unit cell 介紹 ............ 4
2.2 6T、8T 與 loadless 4T-SRAM 操作與架構介紹....... 7
2.2.1 傳統 6T-SRAM 操作與架構介紹...... 7
2.2.2 8T-SRAM 操作與架構介紹....................... 8
2.2.3 Loadless 4T-SRAM 架構與操作.............. 9
2.3 Loadless 4T-SRAM 優勢與劣勢..............11
2.4 實驗設置....................12
第 3 章 Current level of 2kb Loadless 4T-SRAM TRNG array. 23
3.1 介紹................................................23
3.2 Unit cell 架構 .....................................24
3.3 2kb Loadless 4T-SRAM array 架構 ...............25
3.4 Sensing Amplifier 架構.......................25
3.5 3-to-8 Decoder 架構 ..........................26
3.6 2-to-1 multiplexer .............................26
3.7 PISO.................................................27
3.8 設計流程與操作設定.....................27
第 4 章模擬結果.....................................37
4.1 SNM 模擬圖..................................37
4.2 Monte Carlo 模擬圖 .....................37
4.3 Post-sim..................................37
第 5 章量測結果...............................43
5.1 介紹....................................43
5.2 Program shmoo plot .....................44
5.3 MOSAIC plot...............................44
5.4 Inter Hamming Distance plot...............45
5.5 Intra Hamming Distance plot...............45
5.6 Hamming Weight plot ......................46
5.7 Autocorrelation plot .....................46
5.8 NIST Test.................................47
5.9 Output waveform ..........................47
第 6 章總結 ..................................65
參考文獻.......................................71

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指導教授

謝易叡(E-Ray Hsieh)

審核日期

2022-10-25

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