基於自旋轉移矩磁阻式隨機存取記憶體之運算記憶體測試

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姓名

黃代佑(Tai-Yu Huang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

基於自旋轉移矩磁阻式隨機存取記憶體之運算記憶體測試
(Testing of STT-MRAM-Based Computing-In-Memories)

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至系統瀏覽論文 (2030-1-17以後開放)

摘要(中)

隨著資料密集型應用的快速發展，傳統的馮諾曼架構面臨記憶體牆問題。記憶體運算 (CIM) 架構是克服記憶體牆問題的一個很好的替代方案。CIM 架構可以以記憶體模式或運算模式運作。自旋轉移矩磁阻式隨機存取記憶體（STT-MRAM）是新興的非揮發性記憶體之一，被認為是實現 CIM 的良好候選者。為了減少 STT-MRAM 的寫入時間，提出了針對 MTJ 的替代寫入方案，即自旋霍爾輔助自旋轉移矩磁阻式隨機存取記憶體（SAS-MRAM）利用自旋軌道矩（SOT）機制來實現。本論文針對具有儲存和邏輯運算功能的基於 STT-MRAM 和 SAS-MRAM 的 CIM 進行了故障建模，並提出了March 測試來檢測儲存故障和運算故障。首先，透過為基於 1TIMTJ STT-MRAM 的CIM 架構注入單元內和單元間電氣缺陷來執行故障建模。定義了幾種記憶體和計算故障，包括靜態和動態故障。然後，提出了 18N March 測試演算法和（18 +4n1 + 2n2）N March 測試演算法來涵蓋靜態和動態故障。其次，透過為基於 2TIMTJ SAS-MRAM 的 CIM 注入單元內和單元間電氣缺陷來執行故障建模。定義了一個新的故障。然後，提出了一種 (13 +2n)N March 測試演算法來覆蓋基於 SAS-MRAM 的 CIM 的記憶體和計算故障。

摘要(英)

With the rapid development of data-intensive applications, the conventional Von Neumann architecture suffers from the memory wall problem. Computing-in-memory (CIM) architecture is one good alternative to overcome the memory wall issue. CIM architecture can be operated in memory mode or computing mode. Spin-transfer torque magnetic random access memory (STT-MRAM) is one of the emerging non-volatile memories, which is considered as a good candidate to implement CIM. To reduce the STT-MRAM write time, alternative write scheme for MTJ is demonstrated that Spin-Hall-assisted Spin-Transfer Torque Magnetic Random Access Memory (SAS-MRAM) uses spin orbit torque (SOT) mechanism to implement. In this thesis, fault modeling is executed for STT-MRAM and SAS-MRAM-based CIMs with memory and logic operation functions, and March tests are proposed to detect memory faults and computing faults. First, fault modeling is executed by injecting intra-cell and inter-cell electrical defects for 1TIMTJ STT-MRAM-based CIM architecture. Several memory and computing faults are defined, including static and dynamic faults. Then, a 18N March test algorithm and a (18 + 4n1 + 2n2)N March test algorithm are proposed to cover static and dynamic faults. Second, fault modeling is executed by injecting intra-cell and inter-cell electrical defects for 2TIMTJ SAS-MRAM based CIMs. One new fault is defined. Then, a (13 + 2n)N March test algorithm is proposed to cover memory and computing faults of SAS-MRAM-based CIMs.

關鍵字(中)

★ 自旋轉移矩磁阻式隨機存取記憶體
★ 運算記憶體
★ 測試

關鍵字(英)

★ STT-MRAM
★ Computing-In-Memories
★ Testing

論文目次

中文摘要/Chinese abstract i
英文摘要/English abstract i
目次/Table of contents
1 Introduction 1
1.1 MRAM-based Computing-In-Memory 1
1.2 Spin-Transfer Torque Magnetic Random Access Memory 2
1.3 Spin-Hall-assisted Spin-Transfer Torque Magnetic Random Access Memory 7
1.4 Testing of Computing-In-Memories 10
1.5 Motivation 10
1.6 Contribution 11
1.7 Thesis Organization 12
2 Testing of 1T1MTJ STT-MRAM-based Computing-In-Memories 13
2.1 1T1MTJ STT-MRAM-based CIMs 13
2.2 Fault Modeling 14
2.2.1 Simulation model 14
2.2.2 Electrical Defects 19
2.2.3 Fault Modeling Flow 21
2.3 Test Development 25
2.3.1 Existing Fault Models 25
2.3.2 Pattern Dependent Faults, Computing Faults, and Dynamic Faults 26
2.3.3 Fault Analysis 31
2.3.4 Test Algorithm 39
2.4 Summary 55
3 Testing of 2T1MTJ SAS-MRAM-based Computing-In-Memories 57
3.1 2T1MTJ SAS-MRAM CIMs 57
3.2 Simulation model and Electrical Defects 57
3.2.1 Simulation model 57
3.2.2 Electrical Defects 61
3.3 Test Development 66
3.3.1 Fault Analysis 66
3.3.2 Test Algorithm 70
3.4 Summary 75
4 Conclusion and FutureWork 77
Reference 78

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pp. 7–12.

指導教授

李進福(Jin-Fu Li)

審核日期

2025-1-20

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