以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：133

、訪客IP：3.145.65.167

姓名	王子穎(Tzu-Ying Wang)  查詢紙本館藏	畢業系所	電機工程學系
論文名稱	通過虛擬源極傳輸模型對16-nm應變矽鰭式場效電晶體低溫準彈道傳輸的電性變化建模 (Enhanced Cryogenic Quasi-Ballistic Transport in 16-nm Strained Silicon FinFETs by the Spice Assisted Virtual Source Modeling from Device to Circuit Level)
檔案	[Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   至系統瀏覽論文 (2027-10-21以後開放)
摘要(中)	隨著科技的進步，太空產業以及太空元件已經是不可或缺的技術，太空元件需要克服極端的特性，例如非常大的高低溫差、高輻射、真空環境散熱系統都是挑戰。另外量子電腦的推出，使得量子元件的研究需求大量增加，低溫 (Cryogenic Temperature) 金屬氧化物半導體場效電晶體 (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET)元件廣泛的應用於量子元件，如何有效的讓系統表現符合預期，首先我們必須先對元件在不同極端狀況下的電性改變有所認識，進而將結果應用於電路中。在半導體的演進中，半導體的尺寸微縮隨著摩爾定律變化，較少相關研究專注於半導體的低溫特性分析，本研究對十六奈米的應變矽鰭式場效電晶體 (Fin Field-Effect Transistor, FinFETs) 展開低溫特性分析之研究，接著利用量測數據建構積體電路通用模式 (Simulation Program with Integrated Circuit Emphasis, SPICE)，最後透過SPICE模擬低溫特性中電路特性的變化。 本文提出十六奈米應變矽鰭式場效電晶體低溫準彈道傳輸電性的分析技術，載子在通道中飄移、散射、彈道傳輸是主要傳輸機制，根據文獻紀載通道長度小於10nm的元件彈道傳輸主導載子傳輸系統。通道介於10nm~100nm，彈道傳輸也大部分主導載子傳輸，但飄移、散射的影響力也不可忽視。這邊我們會說他處於準彈道傳輸 (Quasi-Ballistic Transport) 狀態，飄移、散射的特性可以藉由有效電子、電洞遷移率分析，本文利用電容-電壓量測 (Capacitance-Voltage Measurement) 計算出有效電子、電洞遷移率，我們可以發現隨著溫度降低，等效氧化層厚度 (Equivalent Oxide Thickness, EOT) 跟著減少至收斂。由於pFinFETs採用矽化鍺 (Silicon-germanium, SiGe) 做為源極和汲極的材料，電洞遷移率在低溫時將會大幅提升。有效遷移率的散射機制也在討論範圍包括聲子、表面、遙控 (remote) 散射機制。對彈道傳輸而言，本文使用虛擬源極傳輸模型 (Virtual Source Model, VSM) 萃取載子入射速度 (Injection Velocity) 以及源極-汲極電阻 (Source-Drain Resistance) 。載子入射速度隨著溫度降低而升高，pFinFETs改變較nFinFETs變化明顯。源極-汲極電阻在pFinFETs較nFinFETs大，主因是pFinFETs的源極-汲極使用SiGe而nFinFETs的源極-汲極使用Si。 分析低溫FinFETs的特性後，藉由量測數據分析的參數建立FinFETs的SPICE模型，這邊採用VSM模型，VSM模型使用量測數據與公式計算的擬合數據匹配，確認模型的準確度，進而推算Injection Velocity以及Source-Drain Resistance用以分析準彈道傳輸，最後藉由SPICE模擬反相器 (Inverter) 、 反或閘 (NOR) 、 反及閘 (NAND) 分析電路在低溫的電性變化。 綜合上述，本實驗首先透過16-nm FinFETs分析出低溫的準彈道傳輸特性，接著利用元件特性建構出的低溫應變矽準彈道傳輸之鰭式場效電晶體模型。並以此模型為基礎，分析電路層級中低溫的變化。 關鍵字： 鰭式場效電晶體、準彈道傳輸、虛擬傳輸模型、低溫、積體電路通用類比程式
摘要(英)	Through advancement of technology, space industry and space devices have become indispensable technologies. Space components need to overcome extreme characteristics in universe, such as huge temperature differences, strong radiation, and vacuum environmental cooling systems. Moreover, introduction of quantum computers has greatly increased the research demand for quantum electronic devices, and cryogenic temperature MOSFET devices are widely used in quantum devices. How can we make the system performance more effective? We must firstly understand electrical variability of devices under environmental extreme conditions, and then apply them and design in the circuit. With assistance of measurement data and the model of the Simulation Program Integrated Emphasis (SPICE) , the characteristics of the circuit in the cryogenic temperature characteristic can be simulated by SPICE. In this paper, a strained silicon technology for cryogenic-temperature quasi-ballistic transport of 16 nm fin field effect transistors is proposed. Carrier drift, diffusion, and ballistic transport in the channel are main mechanisms of transport. Ballistic transport of devices with a channel length less than 10 nm dominates the carrier transport system. In the channel length between 10 nm and 100 nm, ballistic transport also plays an important rule in the carrier transport, but influence of drift and diffusion are still significant, known as the quasi-ballistic transport. Characteristics of drift and diffusion can be analyzed by the effective electron and hole mobility. In this paper, capacitance-voltage measurement is used to calculate effective electron and hole mobility. Then, we can find that with reduction of temperature, the equivalent oxide thickness (EOT) also reduces. Since the p-type FinFETs use silicon germanium (SiGe) as the source and drain material, the hole mobility increases significantly at cryogenic temperatures. Scattering mechanisms for effective mobility are also discussed, including phonon, surface, and remote scattering mechanisms. For ballistic transport, this paper uses the virtual source model (VSM) to extract the carrier injection velocity and source-drain resistance. The carrier injection velocity increases as the temperature decreases. That of the p-type FinFETs increases much more than that of n-type one. The source-drain resistance of the p-type one is larger than that of the n-type one in the cryogenic temperature, since SiGe is used for the source-drain of the p-type and Si is used for the source-drain of the n-type. After the characteristics of the FinFETs at cryogenic-temperature have been analyzed, we use these results to construct an analytic model for simulation. The VSM model uses measured electrical properties of the FinFET, and then estimates the injection velocity and source-drain resistance by fitting measured data with calculated data. Next, we deploy this model into the Spice tool to simulate the electric characteristics of the inverter, NOR, NAND, and then analyze the impact of cryogenic temperature on the circuit. Finally, this experiment first analyzes the quasi-ballistic transport characteristics of cryogenic temperature through 16-nm FinFETs, and then the cryogenic temperature strained silicon FinFETs model is constructed based on our measured device characteristics to predict electrical variations of cryogenic temperature in the circuit level. Keywords: fin field effect transistors, quasi-ballistic transport, virtual source model, cryogenic temperature, Simulation Program with Integrated Circuit Emphasis
關鍵字(中)	★ 鰭式場效電晶體 ★ 準彈道傳輸 ★ 虛擬傳輸模型 ★ 低溫 ★ 積體電路通用類比程式	關鍵字(英)	★ fin field effect transistors ★ quasi-ballistic transport ★ virtual source model ★ cryogenic temperature ★ Simulation Program with Integrated Circuit Emphasis
論文目次	摘要 I Abstract III 致謝 V 圖目錄 VIII 表目錄 X 一、 導論 1 1-1背景 1 1-2研究動機 2 1-3低溫電子學 3 1-4論文架構 3 二、 實驗規劃以及元件介紹 5 2-1鰭式場效電晶體(FinFETs) 5 2-2應變矽鰭式場效電晶體(Strained Silicon FinFETs) 6 2-3實驗規劃與測量儀器 6 三、 低溫鰭式場效電晶體元件特性分析 10 3-1低溫FinFETs電性分析 10 3-2 互補FinFETs的有效遷移率 11 四、 鰭式場效電晶體虛擬傳輸模型的建立 25 4-1 介紹 25 4-2 虛擬傳輸模型 25 4.3鰭式場效電晶體建立結果 27 五、 低溫FinFETs的準彈道傳輸分析 38 5-1 準彈道傳輸 38 5-2 低溫FinFETs準彈道傳輸結果 38 5-3 VSM的分析結果 39 六、 元件VSM模擬電路層級 46 6-1 建立SPICE元件模型 46 6-2 SPICE模擬結果 46 七、 總結與結論 52 Reference 53
參考文獻	[1] Hua Yu Gou, Yu Chen, Mian Gang Tang, Rui Bin Zhao, Xin Shuai Tan, and Li Yan, "Dynamic-Switching Energy Dissipation Behaviorsof Cryogenic Power MOSFET at 77 K," IEEE Transactions on Applied Superconductivity, vol. 31, no. 8, Nov. 2021. [2] Arnout Beckers, Farzan Jazaeri, Andrea Ruffino, Claudio Bruschini, Andrea Baschirotto, and Christian Enz, "Cryogenic Characterization of 28 nm Bulk CMOS Technology for Quantum Computing, " European Solid-State Device Research Conference, pp. 62-65, Sep. 2017 [3] Davide Braga, Shaorui Li, and Farah Fahim, "Cryogenic Electronics Development for High-Energy Physics: An Overview of Design Considerations, Benefits, and Unique Challenges," IEEE Solid-State Circuits Magazine, vol. 13, no. 2, pp. 36-45, Spring 2021. [4] Arnout Beckers, Farzan Jazaeri, and Christian Enz, "Inflection Phenomenon in Cryogenic MOSFET Behavior," IEEE Transactions on Electron Devices, vol. 67, no. 3, pp. 1357-1360, March 2020. [5] Andrea Ruffino, Yatao Peng, Fabio Sebastiano, Masoud Babaie, and Edoardo Charbon, "A 6.5-GHz cryogenic all-pass filter circulator in 40-nm CMOS for quantum computing applications," IEEE Radio Freq. Integr.Circuits Symp (RFIC), pp. 107–110, Jun. 2019. [6] Shirin Montazeri, Wei-Ting Wong, Ahmet H. Coskun, and Joseph C. Bardin, "Ultra-Low-Power Cryogenic SiGe Low-Noise Amplifiers: Theory and Demonstration," IEEE Transactions on Microwave Theory and Techniques, vol. 64, no. 1, pp. 178–187, Jan. 2016. [7] Bishnu Patra, Rosario M. Incandela, Jeroen P. G. van Dijk, Harald A. R. Homulle, Lin Song, Mina Shahmohammadi, Robert Bogdan Staszewski, Andrei Vladimirescu, Masoud Babaie, Fabio Sebastiano, and Edoardo Charbon, "Cryo-CMOS Circuits and Systems for Quantum Computing Applications,"IEEE Journal of Solid-State Circuits, vol. 53, no. 1, pp. 309-321, Jan. 2018. [8] E. Schriek, F. Sebastiano and E. Charbon, "A Cryo-CMOS Digital Cell Library for Quantum Computing Applications," IEEE Solid-State Circuits Letters, vol. 3, pp. 310-313, 2020. [9] S. Bonen, U. Alakusu, Y. Duan, M. J. Gong, M. S. Dadash, L. Lucci, D. R. Daughton, G. C. Adam, S. Iordănescu;M. Pǎşteanu, I. Giangu, H. Jia, L. E. Gutierrez, W. T. Chen, N. Messaoudi, D. Harame, A. Müller, R. R. Mansour, P. Asbeck, and S. P. Voinigescu, "Cryogenic Characterization of 22-nm FDSOI CMOS Technology for Quantum Computing ICs," IEEE Electron Device Letters, vol. 40, no. 1, pp. 127-130, Jan. 2019. [10] Yuan Chen, Lynett Westergard, Curtis Billman, Rosa Leon, Tuan Vo, Mark White, Mohammad Mojarradi, and Elizabeth Kolawa, "Cryogenic Reliability Impact on Analog Circuits at Extreme Low Temperatures," IEEE International Reliability Physics Symposium Proceedings, pp. 156-160, 2007. [11] A. Grill, E. Bury, J. Michl, S. Tyaginov, D. Linten, T. Grasser, B. Parvais, B. Kaczer, M. Waltl, and I. Radu, "Reliability and Variability of Advanced CMOS Devices at Cryogenic Temperatures," IEEE International Reliability Physics Symposium (IRPS), pp. 1-6, 2020. [12] M. Song, K. P. MacWilliams, and J. C. S. Woo, "Comparison of NMOS and PMOS hot carrier effects from 300 to 77 K," IEEE Transactions on Electron Devices, vol. 44, no. 2, pp. 268-276, Feb. 1997. [13] W. Chakraborty, U. Sharma, S. Datta and S. Mahapatra, "Hot Carrier Degradation in Cryo-CMOS," IEEE International Reliability Physics Symposium (IRPS), pp. 1-5, 2020. [14] R. L. Anderson, "The case for cryoelectronics," First International Caracas Conference on Devices, Circuits and Systems, pp. 1-5, 1995. [15] Michele Spasaro, Shai Bonen, Gregory Cooke, Thomas Jager, Tan D. Nhut, Dario Sufra, Sorin P. Voinigescu, Domenico Zito, "Cryogenic Compact Low-Power 60GHz Amplifier for Spin Qubit Control in Monolithic Silicon Quantum Processors," IEEE/MTT-S International Microwave Symposium - IMS, pp. 164-167, 2022. [16] P. Crozat, D. Bouchon, J. C. Henaux, F. Aniel, R. Adde and G. Vernet, "Cryogenic on-chip high frequency device characterization," ESSDERC ′93: 23rd European solid State Device Research Conference, pp. 531-534, 1993. [17] D. Frank, S. Laux, and M. Fischetti, "Monte Carlo Simulation of a 30 nm Dual-gate MOSFET: How Shor Can Si Go?," International Technical Digest on Electron DevicesMeeting, San Francisco, CA, pp 2.1.1-2.1.4, 1992. [18] H. S. Wong, D. J. Frank, and P. M. Solomon, "Device Design Consideration forDouble-gate, Ground-plane, and Single-gate Ultra-thin SOI MOSFETs at the 25 nmChannel Length Generation," International Electron Devices Meeting TechnicalDigest, Safransico, CA, pp. 407-410, 1998. [19] A. Gill, C. Madhu and P. Kaur, "Investigation of short channel effects in Bulk MOSFET and SOI FinFET at 20nm node technology," Annual IEEE India Conference (INDICON), pp. 1-4, 2015. [20] Qintao Zhang, Cindy Wang, Hailing Wang, Christopher Schnabel, Dae-Gyu Park, Scott K. Springer, and Effendi Leobandung, "Experimental Study of Gate-First FinFET Threshold-Voltage Mismatch," IEEE Transactions on Electron Devices, vol. 61, no. 2, pp. 643-646, Feb. 2014. [21] P. Jay and A. D. Darji, "Analysis of the source/drain parasitic resistance and capacitance depending on geometry of FinFET," Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), pp. 298-301, 2015. [22] Arnout Beckers, Farzan Jazaeri, and Christian Enz, "Theoretical Limit of Low Temperature Subthreshold Swing in Field-Effect Transistors," IEEE Electron Device Letters, vol. 41, no. 2, pp. 276-279, Feb. 2020. [23] Katia R. A. Sasaki, Eddy Simoen, Cor Claeys, and Joao A. Martino, "DIBL in enhanced dynamic threshold operation of UTBB SOI with different drain engineering at high temperatures," Symposium on Microelectronics Technology and Devices (SBMicro), pp. 1-4, 2016. [24] H. E. Ghitani, "DIBL coefficient in short-channel NMOS transistors," Proceedings of the Sixteenth National Radio Science Conference. NRSC′99 (IEEE Cat. No.99EX249), pp. D4/1-D4/5, 1999. [25] Naoyoshi Tamura, Yosuke Shimamune and Hirotaka Maekawa, "Embedded silicon germanium (eSiGe) technologies for 45nm nodes and beyond," International Workshop on Junction Technology, pp. 73-77, 2008. [26] C. T. Hsu, M. M. Lau, Y. T. Yeow and Z. Q. Yao, "Analysis of hot-carrier-induced degradation in MOSFETs by gate-to-drain and gate-to-substrate capacitance measurements," IEEE International Reliability Physics Symposium Proceedings, pp. 98-102, 2000. [27] S. Trabelsi, "Frequency and temperature dependence of dielectric properties of chicken meat," IEEE International Instrumentation and Measurement Technology Conference Proceedings, pp. 1515-1518, 2012. [28] J.-P. Colinge, A.J. Quinn, L. Floyd, G. Redmond, J.C. Alderman, Weize Xiong, C.R. Cleavelin, T. Schulz, K. Schruefer, G. Knoblinger, and P. Patruno, "Low-temperature electron mobility in Trigate SOI MOSFETs," IEEE Electron Device Letters, vol. 27, no. 2, pp. 120-122, Feb. 2006. [29] Hiroshi Oka, Takumi Inaba, Shota Iizuka, Hidehiro Asai, Kimihiko Kato, and Takahiro Mori, "Effect of Conduction Band Edge States on Coulomb-Limiting Electron Mobility in Cryogenic MOSFET Operation," IEEE Symposium on VLSI Technology and Circuits, pp. 334-335, 2022. [30] Kensuke Ota, Masumi Saitoh, Yukio Nakabayashi, Takamitsu Ishihara, Toshinori Numata, and Ken Uchida, "Threshold voltage shift and drain current degradation by NBT stress in Si (110) pMOSFETs," Proceedings of the European Solid State Device Research Conference, pp. 134-137, 2010. [31] Ali Khakifirooz, Osama M. Nayfeh, and Dimitri Antoniadis, "A Simple Semiempirical Short-Channel MOSFET Current–Voltage Model Continuous Across All Regions of Operation and Employing Only Physical Parameters," IEEE Transactions on Electron Devices, vol. 56, no. 8, pp. 1674-1680, Aug. 2009. [32] Shaloo Rakheja, Mark S. Lundstrom, and Dimitri A. Antoniadis, "An Improved Virtual-Source-Based Transport Model for Quasi-Ballistic Transistors—Part I: Capturing Effects of Carrier Degeneracy, Drain-Bias Dependence of Gate Capacitance, and Nonlinear Channel-Access Resistance," IEEE Transactions on Electron Devices, vol. 62, no. 9, pp. 2786-2793, Sept. 2015. [33] SÉbastien Martinie, Gilles Le Carval, Daniela Munteanu, S. Soliveres, and Jean-Luc Autran, "Impact of Ballistic and Quasi-Ballistic Transport on Performances of Double-Gate MOSFET-Based Circuits," IEEE Transactions on Electron Devices, vol. 55, no. 9, pp. 2443-2453, Sept. 2008. [34] N. Serra, P. Palestri, G.D.J. Smit, and L. Selmi, "The impact of increased deformation potential at MOS interface on quasi-ballistic transport in ultrathin channel MOSFETs scaled down to sub-10 nm channel length," IEEE International Electron Devices Meeting, pp. 12.1.1-12.1.4, 2013. [35] Hideaki Tsuchiya and Shin-ichi Takagi, "Influence of Elastic and Inelastic Phonon Scattering on the Drive Current of Quasi-Ballistic MOSFETs," IEEE Transactions on Electron Devices, vol. 55, no. 9, pp. 2397-2402, Sept. 2008. [36] N. Serra, P. Palestri, G. D. J. Smit and L. Selmi, "The impact of longitudinal nonuniform fin-thickness on quasi-ballistic transport in FinFETs," 2008 9th International Conference on Ultimate Integration of Silicon, pp. 75-78, 2008.
指導教授	謝易叡 郭明庭(Eray Hsieh Kuo, David M. T.)	審核日期	2022-10-26
推文	facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu
網路書籤	Google bookmarks   del.icio.us   hemidemi   myshare