H2電漿處理之超薄IGZO種子層的低電壓 鐵電電容器以實現30ns/3V讀寫速度且高儲存密度之每單元3位元FeNAND快閃記憶體

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劉承瑞(Cheng-Rui Liu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

H2電漿處理之超薄IGZO種子層的低電壓鐵電電容器以實現30ns/3V讀寫速度且高儲存密度之每單元3位元FeNAND快閃記憶體
(H2 Plasma Treatment in IGZO-Based FeCAP for Enhancing Storage Capacity, Switching Speed, and Endurance/Retention)

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摘要(中)

在本研究中，我們使用In-Ga-Zn-O (IGZO)通道材料與超晶格HfO_2/ZrO_2（SL-HZO）結合，搭配3000W低熱預算的微波退火技術，製造了nearly wake-up free之金屬-鐵電-半導體-金屬（MFSM）電容器。為了消除在ALD生長過程中的碳汙染，我們使用H_2電漿實現了高品質的IGZO/HZO界面，並被X射線光電子能譜學(XPS)證實。經過遠程氫電漿處理提升了極化量Pr與矯頑場Ec，達到了2Pr: 40 μC/cm2 及 Ec: 2.33 MV/cm，使其實現了低功耗 30ns 的寫入速度與均勻的 8 state-per-cell 的儲存密度。高品質的介面確保了 10^8次循環的耐久性以及在超過90°C 溫度下穩定的10年數據保存能力。這種閘級堆疊結構為未來AI記憶計算提供了一條新的途徑。

摘要(英)

In this study, we integrated IGZO channel with a superlattice of HfO_2/ZrO_2 (SL-HZO) under low-thermal-budget microwave annealing to produce a nearly wake-up free ferroelectric capacitors (FeCAP). To eliminate the impact of trap-charges during the atomic layer deposition (ALD) process, we conducted H_2 plasma treatment to eliminate leak defects induced by carbon contamination and maintain neutrality to achieve high-quality IGZO/HZO interfaces, confirmed by X-ray photoelectron spectroscopy (XPS). The H_2 plasma treatment improved polarization (Pr) and coercive field (Ec), reaching 2Pr: 40 μC/cm^2 and Ec: 2.33 MV/cm, enabling a low-power writing speed of 30ns with 8 states (3 bits per cell). The defect engineering method ensures endurance of up to 10^8 cycles and retains 10-year data storage at 90°C. This research provides a new avenue for improving emerging oxide interfaces controlled by ferroelectric polarization.

關鍵字(中)

★ 鐵電記憶體
★ 鐵電電容
★ 銦鎵鋅氧化物
★ 多位元儲存器

關鍵字(英)

★ FeNAND
★ FeCAP
★ IGZO
★ MLC storage

論文目次

摘要 ..................................................... I
ABSTRACT................................................. II
致謝.....................................................III
目錄 ......................................................V
圖目錄 ................................................. VII
第一章序論與文獻回顧 ..................................... 1
1.1 鐵電 .............................................. 1
1.1.1 傳統鐵電材料與現今鐵電薄膜 ....................... 1
1.1.2 記憶體應用 ..................................... 3
1.2 鐵電極化機制模型 .................................... 5
1.3 新穎氧化鉿鋯鐵電薄膜(FE-HF1-XZRXO2, HZO) .............. 6
1.3.1 氧空缺、喚醒與疲勞效應 ........................... 6
1.3.2 電荷捕捉效應、去極化電場與印痕效應 ................ 7
1.4 金屬氧化物通道 ..................................... 9
1.4.1 金屬氧化物半導體的特性與應用.......................... 9
1.4.2 鐵電材料與金屬氧化物通道的結合 ...................... 10
第二章實驗製程 .......................................... 31
2.1 製程流程 ............................................ 31
2.2 薄膜製程 ............................................ 31
2.3 黃光製程 ............................................ 32
2.4 蝕刻製程 ............................................ 32
2.5 低熱預算退火製程、氫電漿處理 .......................... 33
第三章鐵電電容電性量測 ................................... 40
3.1 PUND量測技術 ........................................ 40
3.2 高溫保留度測試 ....................................... 40
3.3 多層儲存單元操作量測 ................................. 41
3.4耐久度評估 ........................................... 41
3.5 切換速度量測方法 ..................................... 42
第四章實驗結果與討論 .................................... 48
4.1 超晶格層狀堆疊HZO .................................... 48
4.2 遠程氫電漿處理對鐵電材料的影響 ........................ 49
4.2.1 極化表現分析 ....................................... 49
4.2.2 高溫保留度分析 ..................................... 50
4.2.3 鉿/鋯亞氧化物比例影響分析 ........................... 51
4.2.4 碳含量變化分析 ..................................... 51
4.2.5 高可靠度三層儲存單元操作 ............................ 52
4.2.6 耐久性影響 ........................................ 52
4.3 極化切換動力學分析 ................................... 53
第五章結論與未來展望 .................................... 65
參考文獻 ................................................ 66

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指導教授

唐英瓚(Ying-Tsan Tang)

審核日期

2024-4-19

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