高速、低能耗、微型1T-PMOS TRNG陣列的設計和特性描述

、線上人數：128

、訪客IP：18.191.168.29

姓名	黃韶翊(SHAO-YI HUANG) 查詢紙本館藏	畢業系所	電機工程學系
論文名稱	高速、低能耗、微型1T-PMOS TRNG陣列的設計和特性描述 (Design and Characterization of High-speed Low- energy consumption Ultra-scaled 1T-PMOS TRNG Array)
檔案	[Endnote RIS 格式] [Bibtex 格式] [相關文章] [文章引用] [完整記錄] [館藏目錄] 至系統瀏覽論文 (2029-6-30以後開放)
摘要(中)	在數位時代，真隨機數對於加密和通訊至關重要。傳統的真隨機數生成器依賴於物理現象，如熱噪音或量子效應，通常需要昂貴的硬件。本研究探討了 CMOS 設備閾值電壓（Vth）的固有變化，以生成高質量的隨機數，提供了一種適用於嵌入式系統的成本效益高的替代方案。我們提出了 40 奈米邏輯 CMOS 技術和 1T 單元，來創建一個 1k-bits 的 TRNG 陣列。這利用 Vth 的微小電性變化作為熵源。TRNG 陣列的加密參數在不同溫度下進行了測試，評估其對安全應用的適用性。實驗使用了四種閾值電壓類型：Hvt 通道長度 40nm(hvt_40nm)、Svt 通道長度 45nm(svt_45nm)、Svt 通道長度 40nm(svt_40nm)和 Lvt 通道長度 40nm(lvt_40nm)，每種單元形成一個 1k-bits 的 TRNG 陣列。這些設置成功地生成了 50％概率的隨機數，操作速度高（10ns），並且能耗低（8.5pJ/bit）。一個 p 型 MOSFET 做為一個單元，該設計每個單元面積僅為 0.1734um2，突顯了其在隨機數生成方面的競爭價值。
摘要(英)	In the digital era, the true random numbers are crucial, especially in encryption and communication. Traditional true random number generators, relying on the phenomena, such as the thermal noise, often require the expensive hardware. This study explores inherent variations in the gate threshold-voltage (Vth) of the CMOS devices to generate high-quality random numbers, providing a cost-effective alternative suitable for embedded systems. We propose the 40nm logic CMOS technology and 1T cells to create a 1-kbit TRNG Array. This utilizes small electrical variations of the Vth as the entropy source. The TRNG Array′s cryptographic parameters were tested under various temperatures, assessing its suitability for secure applications. The experiment used four types of the threshold voltages: the hvt_40nm, svt_45nm, svt_40nm, and lvt_40nm, each FORMing a 1-kbit TRNG Array. These SETups successfully generated random numbers with a 50% probability, operated at high speeds (10-ns operation time), and required low power (8.5pJ/bit). The compact design features a 0.1734-um2 area per cell with one p-type MOSFET, highlighting its competitive value in random number generation.
關鍵字(中)	★ 記憶體	關鍵字(英)
論文目次	目錄摘要..........................................................................................................................................I Abstract...................................................................................................................................II 致謝........................................................................................................................................III 圖目錄...................................................................................................................................IV 表目錄...................................................................................................................................VI 第一章導論...........................................................................................................................1 1-1 背景.............................................................................................................................1 1-2 研究動機.....................................................................................................................2 1-3 TRNG架構回顧.........................................................................................................3 1-3-1 4T- SRAM TRNG.............................................................................................3 1-3-2 RRAM TRNG...................................................................................................6 1-3-3 Ring Oscillator TRNG......................................................................................8 1-4 論文架構...................................................................................................................10 第二章隨機數產生器之電路架構...................................................................................11 2-1 介紹..........................................................................................................................11 2-2 1T-PMOS TRNG unit cell........................................................................................12 2-3 1T-PMOS TRNG Array..........................................................................................12 2-4 Decoder......................................................................................................................14 2-5 Multiplexer................................................................................................................14 2-6 Sensing Amplifier.....................................................................................................18 2-7 Reference cell............................................................................................................18 2-8 設計流程 .................................................................................................................21 第三章模擬驗證.................................................................................................................23 3-1 閥值電壓擾動模擬..................................................................................................23 3-2 晶片隨機數產生模擬.............................................................................................23 第四章真隨機數產生器品質驗證...................................................................................31 4-1實驗設置.....................................................................................................................31 4-2 Shmoo Plot.................................................................................................................33 4-3 MOSAIC Plot ...........................................................................................................36 4-4 Hamming Weight Plot...............................................................................................36 4-5 Intra Hamming Distance............................................................................................39 4-6 Inter Hamming Distance............................................................................................39 4-7 XOR Enhancement Plot.............................................................................................48 4-8 Autocorrelation Plot...................................................................................................48 4-9 Output Waveform......................................................................................................52 4-10 NIST TEST..............................................................................................................52 4-11晶片參數...................................................................................................................55 第五章結論.........................................................................................................................59 參考文獻...............................................................................................................................61
參考文獻	參考資料 [1.1] C. Xu, R. Hu, Y. Wang and F. Shi, "A noniterative reconstruction algorithm for LFSR PRNG," Proceedings of 2012 2nd International Conference on Computer Science and Network Technology, Changchun, China, 2012, pp. 336-339, doi: 10.1109/ICCSNT.2012.6525950. [1.2] C. Martínez-Gómez and I. Baturone, "Calibration of Ring Oscillator PUF and TRNG," 2020 European Conference on Circuit Theory and Design (ECCTD), Sofia, Bulgaria, 2020, pp. 1-4, doi: 10.1109/ECCTD49232.2020.9218444. [1.3] Yabo Qin, "A High-Speed and Self-calibratable True Random Number Generator (TRNG) based on Unified Selector-RRAM," 2023 Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan, 2023, pp. 65-66, doi:10.23919/SNW57900.2023.10183929. [1.4] M. Siswanto and B. Rudiyanto, "Designing of quantum random number generator (QRNG) for security application," 2017 3rd International Conference on Science in Information Technology (ICSITech), Bandung, Indonesia, 2017, pp. 273-277, doi: 10.1109/ICSITech.2017.8257124. [1.5] A. Goyal and V. K. Agarwal, "Low Power Consumption Based 4T SRAM Cell for CMOS 130nm Technology," 2016 8th International Conference on Computational Intelligence and Communication Networks (CICN), 2016, pp. 590-593. [1.6] Yi Sheng Wu, "A 40-nm Loadless 4T-SRAM TRNG MACRO with Read-just-after-write (RAW) Scheme Featuring 5.3Gb/s and 3.64TOP/W," 2023 Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan, 2023, pp. 111-112, doi: 10.23919/SNW57900.2023.10183947. [1.7] V. Kumar and U. Ganguly, "Impact of MIM versus NPN selector on dynamic power in bipolar RRAM Array," 2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS), Jeju, Korea (South), 2014, pp. 1-3, doi: 10.1109/NVMTS.2014.7060864. [1.8] R. Waser, R. Dittmann, G. Staikov, and K. Szot, “Redox-based resistive switching memories – nanoionics mechanisms, prospects, and challenges,” Advanced Materials, vol. 21, pp. 2632 – 2663, 2009, doi: 10.1002/adma.200900375. [1.9] S. Singh, F. Zahoor, G. Rajendran, S. Patkar, A. Chattopadhyay and F. Merchant, "Hardware Security Primitives using Passive RRAM Crossbar Array: Novel TRNG and PUF Designs," 2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, 2023, pp. 449-454. [1.10] J. Cabacinho, J. Casaleiro and L. Oliveira, "Design of a 28nm CMOS Self-Biased Ring Oscillator for Intrinsically Robust PVT TRNG," 2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), Valencia, Spain, 2023, pp. 225-228, doi: 10.1109/PRIME58259.2023.10161976. [1.11] M. A. Prada-Delgado, C. Martínez-Gómez and I. Baturone, "Auto-Calibrated Ring Oscillator TRNG Based on Jitter Accumulation," 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, 2020, pp. 1-4, doi: 10.1109/ISCAS45731.2020.9180598. [2.1] T. Na, B. Song, J. P. Kim, S. H. Kang and S. -O. Jung, "OffSET-Canceling Current-Sampling Sense Amplifier for Resistive Nonvolatile Memory in 65 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 52, no. 2, pp. 496-504, Feb. 2017, doi: 10.1109/JSSC.2016.2612235. [5.1] K. Yang, Q. Dong, Z. Wang, Y. C. Chin, J. Chang, D. Blaauw, D. Svlvester, “A 28NM Integrated True Random Number Generator Harvesting Entropy from MRAM,” 2018 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, 2018, pp. 171-172, doi: 10.1109/VLSIC.2018.8502431. [5.2] K. Yang, D. Blaauw and D. Sylvester, "A robust −40 to 120°C all-digital true random number generator in 40nm CMOS," 2015 Symposium on VLSI Circuits (VLSI Circuits), Kyoto, Japan, 2015, pp. C248-C249, doi: 10.1109/VLSIC.2015.7231275. [5.3] S. Taneja and M. Alioto, “Fully synthesizable unified true random number generator and cryptographic core,” IEEE J. Solid-State Circuits, vol. 56, no. 10, pp. 3049–3061, Oct. 2021. [5.4] Zhigiang Wei, "True random number generator using current difference based on a fractional stochastic model in 40-nm embedded ReRAM," 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2016, pp. 4.8.1-4.8.4, doi: 10.1109/IEDM.2016.7838349. [5.5] W. Y. Yang, B. Y. Chen, C. C. Chuang, E. R. Hsieh, K. S. Li and S. S. Chung, "Novel Concept of Hardware Security in Using Gate-switching FinFET Nonvolatile Memory to Implement True-Random-Number Generator," 2020 IEEE International Electron Devices Meeting (IEDM),2020, pp. 39.3.1-39.3.4. [5.6] S. T. Chandrasekaran, V. E. G. Karnam, and A. Sanyal, “0.36-mW, 52-Mbps true random number generator based on a stochastic delta- sigma modulator,” IEEE Solid-State Circuits Lett., vol. 3, pp. 190–193, 2020. [5.7] V. R. Pamula, X. Sun, S. Kim, F. U. Rahman, B. Zhang, and V. S. Sathe, “An all-digital true-random-number generator with integrated de-correlation and bias correction at 3.2-to-86 Mb/s, 2.58 pJ/bit in 65-nm CMOS,” in Proc. IEEE Symp. VLSI Circuits, Honolulu, HI, USA, Jun. 2018, pp. 1–2. [5.8] M. Akbari et al., "True Random Number Generator Based on the Variability of the High Resistance State of RRAMs," in IEEE Access, vol. 11, pp. 66682-66693, 2023,doi: 10.1109/ACCESS.2023.3290896. [5.9] R. Serrano, C. Duran, M. Sarmiento and C. -K. Pham, "A Unified NVRAM and TRNG in Standard CMOS Technology," in IEEE Access, vol. 10, pp. 79213-79221, 2022, doi: 10.1109/ACCESS.2022.3193639. [5.10] M. Kim, U. Ha, K. J. Lee, Y. Lee, and H.-J. Yoo, “A 82-nW chaotic map true random number generator based on a sub-ranging SAR ADC,” IEEE J. Solid-State Circuits, vol. 52, no. 7, pp. 1953–1965, Jul. 2017.
指導教授	唐英瓚謝易叡	審核日期	2024-7-1
推文	facebook plurk twitter funp google live udn HD myshare reddit netvibes friend youpush delicious baidu
網路書籤	Google bookmarks del.icio.us hemidemi myshare

博碩士論文 110521041 詳細資訊