高功率氮化鎵高電子遷移率電晶體崩潰特性優化研究

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姓名

呂彥鋒(Yen-Feng Lu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

高功率氮化鎵高電子遷移率電晶體崩潰特性優化研究
(Optimization Study on the Breakdown Characteristics of High-Power GaN High Electron Mobility Transistors)

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摘要(中)

本研究的主要目的是優化高功率氮化鎵高遷移率電晶體(GaN HEMT)
之磊晶結構，以提升其垂直崩潰電壓、導電性能和動態電阻表現。首先，
我們通過引入超晶格結構，使磊晶層的垂直崩潰電場從1.75 MV/cm提升
至1.94 MV/cm，並進一步確定了氮化鎵緩衝層中的最佳碳摻雜濃度，最
終在優化超晶格結構後，磊晶層的垂直崩潰電場提升至2.28 MV/cm。基
於此設計的高功率GaN HEMT元件，並結合P型氮化鎵及合適的氮化鋁
鎵位障層，元件在汲極-閘極距離（Lgd）為13 μm的條件下，實現了1351
V@1 mA/mm (1600 V@1 mA/mm, substrate floating)的崩潰電壓、1.2 V 的
閾值電壓，以及1.95 mΩ-cm2的特徵導通電阻，達到國際領先水準。
此外，對下位障層進行鋁含量和厚度的調整，能有效減少通道層內電
場變化，從而顯著改善通道導電率。當下位障層鋁含量由6 %降至2 %，
厚度從100 nm增加至150 nm後，在-100 V基板負偏壓下，通道導電率
的下降程度由78 %顯著減少至38 %。然而，較低鋁含量和較厚的下位障
層結構，雖然在負偏壓下提升了導電性，但動態電阻有所增加。本研究設
計鋁含量6 %、厚度50 nm之下位障層結構在VDSQ為80 V的條件下，動
態電阻由原本的7.54倍下降至4.3倍，動態特性明顯獲得改善。
總結來說，本研究的創新在於通過精確的超晶格結構和下位障層設
計，成功提升了GaN HEMT元件的垂直崩潰電壓、導電性能與動態電阻表現，並提出了根據應用需求靈活設計下位障層的策略，以平衡導電性與
動態電阻，確保元件在高功率操作中的穩定性與效率。

摘要(英)

The primary objective of this research is to optimize the epitaxial structure
of high-power gallium nitride high electron mobility transistors (GaN HEMTs)
in order to enhance their vertical breakdown voltage, electrical conductivity,
and dynamic resistance performance. Initially, the introduction of a superlattice
structure increased the vertical breakdown field of the epitaxial layer from 1.75
MV/cm to 1.94 MV/cm. Through further optimization, the ideal carbon doping
concentration in the GaN buffer layer was identified, eventually raising the
vertical breakdown field of the epitaxial layer to 2.28 MV/cm following the
refinement of the superlattice structure.
Using this optimized design, the fabricated high-power GaN HEMT
devices, incorporating a p-type GaN and a suitable AlGaN barrier layer,
demonstrated a breakdown voltage of 1351 V@1 mA/mm (1600 V@1 mA/mm,
substrate floating), a threshold voltage of 1.2 V, and a specific on-resistance of
1.95 mΩ-cm2 for a gate-to-drain distance (Lgd) of 13 μm, achieving
internationally competitive performance standards.
Additionally, modifying the aluminum content and thickness of the back
barrier layer proved effective in reducing the electric field variation in the
channel layer, thereby substantially improving the channel conductivity. When
the aluminum content in the back barrier was decreased from 6 % to 2 %, and
its thickness increased from 100 nm to 150 nm, the drop in channel conductivity
under a substrate negative bias of -100 V decreased from 78 % to 38 %.
However, while the lower aluminum content and thicker back barrier improved
conductivity under negative bias, the dynamic resistance increased. In this
study, a back barrier structure with 6 % aluminum content and 50 nm thickness reduced the dynamic resistance from 7.54 times to 4.3 times under a VDSQ of
80 V, considerably improving dynamic characteristics.
In summary, the novelty of this work lies in the precise design of
superlattice structures and back barrier layers, which successfully enhance the
vertical breakdown voltage, conductivity, and dynamic resistance performance
of GaN HEMT devices. The study also introduces strategies for flexible back
barrier design tailored to specific application needs, balancing conductivity and
dynamic resistance to ensure device stability and efficiency under high-power
operation conditions.

關鍵字(中)

★ 氮化鎵高電子遷移率電晶體
★ 高功率元件
★ 動態電阻
★ 崩潰電壓
★ 導電率
★ 磊晶

關鍵字(英)

★ GaN HEMT
★ Power Device
★ Dynamic Ron
★ Breakdown voltage
★ Conductivity
★ Epitaxy

論文目次

論文摘要 i
Abstract iii
致謝 v
目錄 vi
圖目錄 x
表目錄 xv
第一章導論 1
1.1 前言 1
1.2 研究背景 2
1.2.1 運用在功率元件上的寬能隙材料介紹 2
1.2.2 自發極化效應 3
1.2.3 壓電極化效應 5
1.2.4 二維電子氣 6
1.3 研究動機 9
1.3.1 前言 9
1.3.2 高功率元件: 崩潰電壓限制 9
1.3.3 高電壓GaN HEMT發展背景 11
1.3.4 實驗設計理念與論文架構 14
1.4 論文架構 15
第二章實驗方法 16
2.1 有機金屬氣相磊晶成長法 16
2.1.1 磊晶設備介紹 16
2.1.2 有機金屬氣相磊晶 17
2.1.3 GaN HEMT磊晶基本結構 19
2.2 磊晶片特性量測機台介紹與方法 21
2.2.1 前言 21
2.2.2 光致發光量測 22
2.2.3 霍爾效應量測 23
2.2.4 表面粗糙度量測 25
2.3 高垂直崩潰電壓緩衝層實驗項目 26
2.3.1 GaN HEMT超晶格緩衝層介紹 26
2.3.2 GaN HEMT超晶格緩衝層設計 28
2.3.3 高阻值碳摻雜氮化鎵緩衝層設計 29
2.3.4 元件崩潰電壓量測機台及方法 30
2.4 下位障層結構實驗項目 31
2.4.1 降低碳摻雜對於元件導電性影響 31
2.4.2 下位障層結構設計 32
2.4.3 元件基板負偏壓量測機台及方法 33
2.5 GaN HEMT常關型元件設計 34
2.5.1 前言 34
2.5.2 導通電阻 34
2.5.3 閾值電壓 37
2.5.4 GaN HEMT常關型元件設計 40
2.6 本章總結 41
第三章結果與討論 42
3.1 提升垂直崩潰電壓 42
3.1.1 超晶格緩衝層結構對於崩潰電壓影響 42
3.1.2 碳摻雜濃度對於崩潰電壓影響 45
3.1.3 高垂直崩潰電壓緩衝層設計實驗 48
3.1.4 高垂直崩潰電壓緩衝層結果 49
3.1.5 本章總結 52
3.2 磊晶片表面粗糙度 55
3.2.1 本章總結 56
3.3 下位障層 57
3.3.1 前言 57
3.3.2 負基板偏壓量測分析 60
3.3.3 下位障層之優化: 負基板偏壓量測 66
3.3.4 動態電阻特性 68
3.3.5 本章總結 71
結論與未來展望 72
參考文獻 74
附錄1 78
附錄2 85

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指導教授

綦振瀛(Jen-Inn Chyi)

審核日期

2024-11-22

推文