X頻段及Ka頻段CMOS多位元開關電容陣列之F類多相位壓控振盪器與鎖相迴路研製

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：79

、訪客IP：18.226.159.73

姓名

陳俊良(Jun-Liang Chen) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

X頻段及Ka頻段CMOS多位元開關電容陣列之F類多相位壓控振盪器與鎖相迴路研製
(Design of X-band and Ka-band CMOS Class-F Multi-Phase Voltage-Controlled Oscillator and Phase-Locked Loop Using Multi-Bit Switched-Capacitor Array)

相關論文

★ 微波及毫米波切換器及四相位壓控振盪器整合除三除頻器之研製	★ 微波低相位雜訊壓控振盪器之研製
★ 高線性度低功率金氧半場效電晶體射頻混波器應用於無線通訊系統	★ 砷化鎵高速電子遷移率之電晶體微波/毫米波放大器設計
★ 微波及毫米波行進波切換器之研製	★ 寬頻低功耗金氧半場效電晶體射頻環狀電阻性混頻器
★ 微波與毫米波相位陣列收發積體電路之研製	★ 24 GHz汽車防撞雷達收發積體電路之研製
★ 低功耗低相位雜訊差動及四相位單晶微波積體電路壓控振盪器之研究	★ 高功率高效率放大器與振盪器研製
★ 微波與毫米波寬頻主動式降頻器	★ 微波及毫米波注入式除頻器與振盪器暨射頻前端應用
★ 寬頻主動式半循環器與平衡器研製	★ 雙閘極元件模型與微波及毫米波分佈式寬頻放大器之研製
★ 銻化物異質接面場效電晶體之研製及其微波切換器應用	★ 微波毫米波寬頻振盪器與鎖相迴路之研製

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

至系統瀏覽論文 (2028-8-8以後開放)

摘要(中)

本論文主要研究使用開關電容陣列及波形整型得到較低相位雜訊的本地振盪源。第二章的主要內容為操作在K頻段及Ka頻段且使用5位元開關電容陣列來達到高可調範圍的差動壓控振盪器。第三章則是先提及將輸出波形整型對相位雜訊的影響，接著再介紹操作在X頻段的F23類差動壓控振盪器，以及提出三顆分別使用背閘極耦合、閘極端電容耦合和汲極端電容耦合的F23類四相位壓控振盪器。第四章為使用第三章所提出的X頻段汲極端電容耦合F23類四相位壓控振盪器作為振盪源實現的X頻段F23類四相位鎖相迴路。
第二章為K/Ka頻段使用開關電容陣列和可開關式可變電容陣列之5位元壓控振盪器。前半部分主要介紹多位元開關電容陣列和可開關式可變電容陣列的設計分析，首先提及KVCO對相位雜訊及鎖相迴路穩定性的影響，帶出KVCO小的情況下要使用開關電容陣列才能夠維持高可調範圍，又因為KVCO小所以有額外設計輔助用可開關式可變電容，確保頻率的連續性。電路架構為最基本的交錯耦合對搭配5位元的開關電容陣列及可開關式可變電容陣列實現一壓控振盪器，此電路使用台積電90 nm CMOS製程實現，可調頻率範圍為22.6~29.8 GHz(27.5%)，整體輸出功率為-6~-7.7 dBm，整體距載波偏移1 MHz相位雜訊在-98~-103.5 dBc/Hz，FoMPN為-184~-184.4 dBc/Hz，FoMT為-192.8~-193.1 dBc/Hz，晶片面積為0.94 × 0.81 mm2。第二章後半部分則是著重說明如何依照業界設計需求，經由經驗及公式計算快速設計位元數，並使用台積電22 nm CMOS製程舉出模擬實例。
第三章為X頻段之F23類四相位壓控振盪器，由時變模型，我們知道要將輸出波形整型成方波才能夠得到較好的相位雜訊，即F類壓控振盪器。又因為Groszkowski effect，所以我們知道要在二倍頻做一個高阻抗降低波形的不對稱性，以此得到較好的相位雜訊，於是最終選擇實作F23類壓控振盪器。首先設計F23類差動壓控振盪器，接著再根據設計完的差動壓控振盪器搭配背閘極耦合、閘極端電容耦合和汲極端電容耦合的方式，實作出F23類四相位壓控振盪器。本章節之電路皆是使用台積電0.18 μm CMOS製程實現，經過量測比較後，我們得知使用汲極端電容耦合的F23類四相位壓控振盪器有較好的電路性能，其可調頻率範圍為10.23~10.89 GHz，整體輸出功率在-6~-8 dBm，整體距離載波偏移1 MHz的相位雜訊在-110.5 ~ -113.8 dBc/Hz，最小的相位誤差以及振幅誤差分別是0.3°和0.1 dB，FoMPN為-181.1 ~ -184.5 dBc/Hz，FoMT為-176.8 ~ -180.2 dBc/Hz，FoMQ約為-202~-228.7 dBc/Hz，晶片面積為0.725 × 1.127 mm2。
第四章為X頻段之F23類四相位鎖相迴路，本章將介紹鎖相迴路的每個子電路之功能及如何運作，接著再分析鎖相迴路的穩定性及突波抑制能力，迴路中的壓控振盪器使用第三章的汲極端電容耦合F23類四相位壓控振盪器。本章節之電路使用台積電0.18 μm CMOS製程實現，壓控振盪器本身的頻率可調範圍為10.51~11.06 GHz，而鎖相迴路之頻率鎖定範圍為10.52~11.06 GHz，幾乎全頻段鎖定，距離載波偏移1 MHz的相位雜訊為−104 dBc/Hz，量測到的最小方均根抖動量為250 fs，抖動的積分範圍為1 kHz到40 MHz。全頻段的突波抑制量皆大於60 dBc，鎖相迴路部分的FoMPN為-166.5 dBc/Hz，FoMjitter為-233.7 dB，FoMN為-251.7 dB，晶片面積為1.05 × 1.614 mm2。

摘要(英)

This paper primarily investigates the use of a switched-capacitor array and waveform shaping to achieve a local oscillator with lower phase noise. Chapter 2 focuses on a K and Ka-band voltage-controlled oscillator (VCO) using a 5-bit switch-capacitor array to achieve high frequency tuning range. Chapter 3 first discusses the impact of waveform shaping on phase noise, and introduces X-band Class-F23 voltage-controlled oscillator. Additionally, it proposes three ways to realize Class-F23 quadrature voltage-controlled oscillators(QVCO), each utilizing back-gate coupling, gate capacitance coupling, and drain capacitance coupling, respectively. Chapter 4 focuses on implementing an X-band Class-F23 quadrature phase-locked loop (PLL) using the X-band quadrature voltage-controlled oscillator with drain capacitance coupling as the oscillator source in Chapter 3.
Chapter 2 is talking about a K/Ka-band 5-bit VCO, which using switch-capacitor array and switchable varactor array. The first half of chapter primarily focuses on the design of multi-bit switch-capacitor arrays and switchable varactor array. First, it metions the impact of the KVCO on phase noise and phase-locked loop stability. When the KVCO is small, the utilization of a switch-capacitor array becomes necessary to maintain a high tuning range, additionally, due to the small KVCO, so I designed auxiliary switchable varactor to ensure frequency continuity. The circuit topology is the fundamental cross-coupled pair with 5-bit switch-capacitor array and switchable varactor array to realize a voltage-controlled oscillator. This circuit is fabricated in TSMC 90 nm CMOS process. The frequency tuning range is from 22.6 to 29.8 GHz(27.5%), the overall output power is from -6 to -7.7 dBm, the overall phase noise at 1 MHz offset frequency is from -98 to -103.5 dBc/Hz, the FoMPN is from -184 to -184.4 dBc/Hz, the FoMT is from -192.8 to -193.1 dBc/Hz, the chip size is 0.94 × 0.81 mm2. The second half of Chapter 2 focuses on explaining how to design bit numbers quickly according to industry design specifications, using experience and formula calculations. It also provides a simulated example using TSMC 22 nm CMOS process.
Chapter 3 is about the design of an X-band Class-F23 quadrature voltage-controlled oscillator. From the time-variant model, we know that shaping the output waveform into a square wave is necessary to achieve better phase noise, which corresponds to an Class-F voltage-controlled oscillator. Additionally, due to the Groszkowski effect, we need to realize a high-impedance at twice the frequency to reduce waveform asymmetry and improve phase noise. Therefore, the final choice is to implement the Class-F23 voltage-controlled oscillator. First, we design a Class-F23 voltage-controlled oscillator. Then, based on the designed voltage-controlled oscillator, we implement a quadrature voltage-controlled oscillator of the Class-F23 using methods such as back-gate coupling, gate capacitance coupling, and drain capacitance coupling, respectively. This circuit is fabricated in TSMC 0.18 μm CMOS process. After the measurment and comparison, we know that the Class-F23 quadrature voltage-controlled oscillator with drain capacitance coupling exhibited better circuit performance. The frequency tuning range is from 10.23 to 10.89 GHz, the overall output power is from -6 to -8 dBm, the overall phase noise at 1 MHz offset frequency is from -110.5 to -113.8 dBc/Hz,the FoMPN is from -181.1 to -184.5 dBc/Hz, the FoMT is from -176.8 to -180.2 dBc/Hz, the FoMQ is from -202 to -228.7 dBc/Hz, the chip size is 0.725 × 1.127 mm2.
Chapter 4 introduces the X-band Class-F23 quadrature phase-locked loop. This chapter will discuss the functions and operating theory of each sub-circuit in the PLL. Furthermore, it will analyze the stability and spur suppression ability of the PLL. The voltage-controlled oscillator in the loop utilizes the quadrature voltage-controlled oscillator with drain capacitance coupling which introduced in Chapter 3. This circuit is fabricated in TSMC 0.18 μm CMOS process. The VCO frequency tuning range is from 10.51 to 11.06 GHz,and the PLL frequency locking range is from 10.52 to 11.06 GHz, almost full frequncy band locking, the phase noise at 1 MHz offset frequency is -104 dBc/Hz. Under the integration range of 1 kHz to 40 MHz, the measured minimum root mean square jitter is 250 fs. The spur suppression throughout the entire frequency band is greater than 60 dBc. The FoMPN is -166.5 dBc/Hz, the FoMjitter is -233.7 dB, the FoMN is -251.7 dB, the chip size is 1.05 × 1.614 mm2.

關鍵字(中)

★ 鎖相迴路
★ 開關電容陣列
★ F類壓控振盪器
★ 四相位壓控振盪器

關鍵字(英)

論文目次

目錄
摘要 II
Abstract IV
目錄 VII
圖目錄 XI
表目錄 XXIII
第一章緒論 1
1.1 研究動機及背景 1
1.2 相關研究發展 2
1.3 論文貢獻 3
1.4 論文架構 3
第二章 K/Ka頻段使用開關電容陣列和可開關式可變電容陣列之5位元壓控振盪器5
2.1 簡介 5
2.2 相位雜訊簡介 5
2.2.1 雜訊與相位雜訊成因[38] 5
2.2.2 非時變模型(Leeson’s model)[39] 8
2.3 電路架構設計與分析 9
2.3.1 可開關式可變電容陣列 10
2.3.2 開關電容陣列 16
2.3.3 電感 26
2.4 類比電路佈局簡介 27
2.4.1 開關電容陣列佈局 28
2.4.2 邏輯反相器佈局 32
2.5 電路實現與量測結果 33
2.6 總結 43
2.7 問題與討論 45
2.8 業界設計實例 48
2.8.1 經驗法則 48
2.8.2 切換式可變電容陣列設計 50
2.8.3 開關電容陣列設計 57
2.8.4 電感設計 63
2.8.5 交錯耦合對電晶體設計 66
2.8.6 可切換式電流源設計 68
2.8.7 緩衝器設計 70
2.8.8 整體電路 71
2.8.9 模擬結果 73
第三章 X頻段之F23類四相位壓控振盪器 75
3.1 簡介 75
3.2 時變模型(脈衝靈敏函數:Impulse Sensitivity Function, ISF)簡介[49] 76
3.3 隱共模諧振(implicit common-mode resonance, ICMR)簡介 82
3.4 F23類壓控振盪器設計 83
3.5 F23類差動壓控振盪器實現與量測結果 94
3.6 F23類四相位壓控振盪器設計 101
3.6.1 F23類背閘極耦合四相位壓控振盪器 102
3.6.2 F23類閘極端電容耦合四相位壓控振盪器 105
3.6.3 F23類汲極端電容耦合四相位壓控振盪器 108
3.7 四相位耦合機制分析 110
3.7.1 閘極端電容耦合 110
3.7.2 汲極端電容耦合 112
3.8 F23類四相位壓控振盪器實現與量測結果 115
3.8.1 相位誤差及振幅誤差量測方法 115
3.8.2 F23類背閘極耦合四相位壓控振盪器量測架設與結果 118
3.8.3 F23類閘極端電容耦合四相位壓控振盪器量測架設與結果 129
3.8.4 F23類汲極端電容耦合四相位壓控振盪器量測架設與結果 140
3.9 總結 151
第四章 X頻段之F23類四相位鎖相迴路 155
4.1 鎖相迴路簡介 155
4.2 子電路簡介 156
4.2.1 壓控振盪器 156
4.2.2 除頻器 157
4.2.3 相位頻率偵測器 158
4.2.4 電荷幫浦 159
4.2.5 迴路濾波器 162
4.3 鎖相迴路迴路分析 163
4.4 鎖相迴路電路實現 168
4.4.1 四相位壓控振盪器 168
4.4.2 電流模式邏輯除頻器 170
4.4.3 差動轉單端緩衝放大器 173
4.4.4 單相位時序除頻器 175
4.4.5 相位頻率偵測器與電荷幫浦 177
4.4.6 迴路濾波器 185
4.5 量測結果 188
4.5.1 自由振盪之結果 191
4.5.2 鎖定之量測結果 198
4.6 總結 205
第五章結論 208
參考文獻 210

參考文獻

[1] 曲建仲，第五代行動通訊(5G)的原理與應用，台灣扶輪，民國110年5月
[2] W. -C. Lai, “Design of 1V CMOS 5.8 GHz VCO with Switched Capacitor Array Tuning for Intelligent Sensor Fusion,” Int’l Conf. on Advanced Robotics and Intelligent Syst. (ARIS), Taipei, Taiwan, 2020, pp. 1-4.
[3] H. Sjoland, “Improved switched tuning of differential CMOS VCOs,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 49, no. 5, pp. 352-355, May 2002.
[4] A. Kral, F. Behbahani and A. A. Abidi, “RF-CMOS oscillators with switched tuning,” in Proc. IEEE Custom Integr. Circuits Conf., May 1998, pp. 555-558.
[5] A. Mazzanti and P. Andreani, “Class-C Harmonic CMOS VCOs, With a General Result on Phase Noise,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2716-2729, Dec. 2008.
[6] Z. Xing, H. Liu, Y. Wu, C. Zhao, Y. Yu and K. Kang, “A 3-GHz Inverse-Coupled Current-Reuse VCO Implemented by 1:1 Transformer,” IEEE Microw. Wireless Compon. Lett., vol. 32, no. 5, pp. 434-436, May 2022.
[7] P. -Y. Wang, G. -Y. Su, Y. -C. Chang, D. -C. Chang and S. S. H. Hsu, “A Transformer-Based Current-Reuse QVCO With an FoM Up to −200.5 dBc/Hz,” IEEE Trans. on Circuits Syst. II, Exp. Briefs, vol. 65, no. 6, pp. 749-753, June 2018.
[8] M. Shahmohammadi, M. Babaie and R. B. Staszewski, “A 1/f Noise Upconversion Reduction Technique for Voltage-Biased RF CMOS Oscillators,” IEEE J. Solid-State Circuits, vol. 51, no. 11, pp. 2610-2624, Nov. 2016.
[9] M. Babaie and R. B. Staszewski, “A Class-F CMOS Oscillator,” IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 3120-3133, Dec. 2013.
[10] X. Liu, J. Jin, C. Yang, Y. Liu and J. Zhou, “A 12-GHz Transformer Feedback Class-F₂,₃ Voltage-Controlled Oscillator Using Noise Circulating With FoM of 190.5 dBc/Hz,” IEEE Microw. Wireless Compon. Lett., vol. 31, no. 11, pp. 1231-1234, Nov. 2021.
[11] T. Wang, W. Li, H. Zhou, J. Ye and Y. Xu, “An 8-12GHz Class-F3 VCO with Multi-LC Tank in 28nm CMOS,” in Proc. IEEE 13th Int. Conf. ASIC, Chongqing, China, 2019, pp. 1-4.
[12] F. Wang and H. Wang, “A Noise Circulating Oscillator,” IEEE J. Solid-State Circuits, vol. 54, no. 3, pp. 696-708, March 2019.
[13] C. Wan, T. Xu, X. Yi and Q. Xue, “A VCO With Extra Cross-Coupling Path,” IEEE Microw. Wireless Compon. Lett., vol. 31, no. 10, pp. 1130-1133, Oct. 2021.
[14] P. Mirajkar, J. Chand, S. Aniruddhan and S. Theertham, “Low Phase Noise Ku-Band VCO With Optimal Switched-Capacitor Bank Design,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 26, no. 3, pp. 589-593, March 2018.
[15] S. Alzahrani, S. Elabd, S. Smith, A. Naguib, R. Tantawy and W. Khalil, “Analysis and Design of the Tank Feedline in Millimeter-Wave VCOs,” IEEE Trans. Microw. Theory Techn., vol. 70, no. 5, pp. 2668-2679, May 2022.
[16] J. -Y. Hsieh and K. -Y. Lin, “A 0.7-mW LC Voltage-Controlled Oscillator Leveraging Switched Biasing Technique for Low Phase Noise,” IEEE Trans. on Circuits Syst. II, Exp. Briefs, vol. 66, no. 8, pp. 1307-1310, Aug. 2019.
[17] Y. Jiang, C. Shen, T. Wu, H. Chen, S. Ma and J. Ren, “A 5-8 GHz Wideband and Low Phase Noise Cross-Coupled LC VCO Using 6-bit DCCA in 40nm CMOS Process,” IEEE Solid-State and Integrated Circuit Technology (ICSICT), Nangjing, China, 2022, pp. 1-3.
[18] G. Li, L. Liu, Y. Tang and E. Afshari, “A Low-Phase-Noise Wide-Tuning-Range Oscillator Based on Resonant Mode Switching,” IEEE J. Solid-State Circuits, vol. 47, no. 6, pp. 1295-1308, June 2012.
[19] H. Zhang and Q. Xue, “Design of Wideband Low Phase Noise Class-C QVCO With Low Amplitude and Phase Errors,” IEEE Microw. Wireless Compon. Lett., vol. 25, no. 11, pp. 724-726, Nov. 2015.
[20] Y. -J. Moon, Y. -S. Roh, C. -Y. Jeong and C. Yoo, “A 4.39–5.26 GHz LC-Tank CMOS Voltage-Controlled Oscillator With Small VCO-Gain Variation,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 8, pp. 524-526, Aug. 2009.
[21] W. Wu et al., “A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO,” IEEE J. Solid-State Circuits, vol. 56, no. 12, pp. 3756-3767, Dec. 2021.
[22] Jaewook Shin et al., “A wideband fractional-N frequency synthesizer with linearized coarse-tuned VCO for UHF/VHF mobile broadcasting tuners,” in Proc. IEEE Asian Solid-State Circuit Conf., Jeju, 2007, pp. 440-443.
[23] C. T. Fu and H. C. Luong, “A 0.8-V CMOS quadrature LC VCO using capacitive coupling,” in Proc. IEEE Asian Solid-State Circuit Conf., Jeju, Korea (South), 2007, pp. 436-439.
[24] U. Decanis, A. Ghilioni, E. Monaco, A. Mazzanti, F. Svelto, “A mm-Wave quadrature VCO based on magnetically coupled resonators,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp.280-282, Feb. 2011.
[25] A. Rofougaran, J. Rael, M. Rofougaran and A. Abidi, “A 900 MHz CMOS LC-oscillator with quadrature outputs,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, USA, 1996, pp. 392-393.
[26] J. -P. Hong, S. -J. Yun, N. -J. Oh and S. -G. Lee, “A 2.2-mW Backgate Coupled LC Quadrature VCO With Current Reused Structure,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 4, pp. 298-300, April 2007.
[27] Hye-Ryoung Kim, Seung-Min Oh, Sung-Do Kim, Young-Sik Youn and Sang-Gug Lee, “Low power quadrature VCO with the back-gate coupling,” IEEE ESSCIRC, Estoril, Portugal, 2003, pp. 699-701.
[28] X. Ding, H. Yu, B. Yu, Z. Xu and Q. J. Gu, “A Superharmonic Injection based G-band Quadrature VCO in CMOS,” in IEEE MTT-S Int. Microw. Symp. Dig., Los Angeles, CA, USA, 2020, pp. 345-348.
[29] Z. Zhang, G. Zhu and C. Patrick Yue, “A 0.65-V 12–16-GHz Sub-Sampling PLL With 56.4-fsrms Integrated Jitter and −256.4-dB FoM,” IEEE J. Solid-State Circuits, vol. 55, no. 6, pp. 1665-1683, June 2020.
[30] Y. Lim et al., “17.8 A 170MHz-Lock-In-Range and −253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, USA, 2020, pp. 280-282.
[31] A. Elkholy, M. Talegaonkar, T. Anand and P. Kumar Hanumolu, “Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers,” IEEE J. Solid-State Circuits, vol. 50, no. 12, pp. 3160-3174, Dec. 2015.
[32] J. Lee and H. Wang, “Study of Subharmonically Injection-Locked PLLs,” IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1539-1553, May 2009.
[33] A. Mahmoud, P. Andreani and P. Lu, “A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise,” in 2015 Nordic Circuits and Systems Conference (NORCAS), Oslo, Norway, 2015, pp. 1-4.
[34] Y. Wang, K. Ma and K. S. Yeo, “A hybrid CMOS clock divider for PLL of 60GHz transceiver,” in 2014 XXXIth URSI General Assembly and Scientific Symposium (URSI GASS), Beijing, China, 2014, pp. 1-4.
[35] R. Wang, J. Li, C. Shi, J. Chen and R. Zhang, “A 25–37GHz VCO Employing Stacked-Coupled Switched Inductor and Co-Tuned Buffer in 55nm CMOS for Multi-Band 5G mmW Applications,” ” in Proc. IEEE 20th Top. Meeting Silicon Monolithic Integr. Circuits RF Syst. (SiRF), San Diego, CA, USA, 2021, pp. 37-39.
[36] Liu Qing, Sun Jiangtao, S. Kurachi, N. Itoh and T. Yoshimasu, “A switched-inductor based VCO with an ultra-wideband tuning range of 87.6 %,” in Proc. IEEE 8th Int. Conf. ASIC, Changsha, China, 2009, pp. 355-358.
[37] P. Agarwal, Partha Pratim Pande and D. Heo, “25.3 GHz, 4.1 mW VCO with 34.8% tuning range using a switched substrate-shield inductor,” in IEEE MTT-S Int. Microw. Symp. Dig., Phoenix, AZ, USA, 2015, pp. 1-4.
[38] B. Razavi, RF Microelectronics, Prentice Hall, 1998.
[39] D. B. Leeson, “A simple model of feedback oscillator noise spectrum,” Proc. IEEE, vol. 54, no. 2, pp. 329-330, Feb. 1966.
[40] Chi-Hung Lin and K. Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm/sup 2/,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1948-1958, Dec. 1998.
[41] J. Zhang, N. Sharma and K. K. O, “21.5-to-33.4 GHz Voltage-Controlled Oscillator Using NMOS Switched Inductors in CMOS,” IEEE Microw. Wireless Compon. Lett., vol. 24, no. 7, pp. 478-480, July 2014.
[42] B. Sadhu, T. Anand and S. K. Reynolds, “A Fully Decoupled LC Tank VCO Topology for Amplitude Boosted Low Phase Noise Operation,” IEEE J. Solid-State Circuits, vol. 53, no. 9, pp. 2488-2499, Sept. 2018.
[43] P. Agarwal et al., “Switched Substrate-Shield-Based Low-Loss CMOS Inductors for Wide Tuning Range VCOs,” IEEE Trans. Microw. Theory Techn., vol. 65, no. 8, pp. 2964-2976, Aug. 2017.
[44] M. Haghi Kashani, R. Molavi and S. Mirabbasi, “A 2.3-mW 26.3-GHz Gm-Boosted Differential Colpitts VCO With 20% Tuning Range in 65-nm CMOS,” IEEE Trans. Microw. Theory Techn., vol. 67, no. 4, pp. 1556-1565, April 2019.
[45] D. Yang, H. Wang, D. Zeng, H. Zheng, L. Zhang and Z. Yu, “Design of a 24GHz low phase-noise,wide tuning-range VCO with optimized switches in capacitor array and bias filtering technique,” IEEE Solid-State and Integrated Circuit Technology (ICSICT), Shanghai, China, 2010, pp. 696-698.
[46] W. Tan, T. Wu, Z. Xing, Y. Peng, H. Liu and K. Kang, “A 21.95-24.25 GHz Class-C VCO for 24 GHz FMCW Radar Applications,” in Proc. IEEE MTT-S Int. Wireless Symp., Guangzhou, China, 2019, pp. 1-3.
[47] E. Hegazi, H. Sjoland and A. A. Abidi, “A filtering technique to lower LC oscillator phase noise,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1921-1930, Dec. 2001.
[48] S. Lee, I. Choi, H. Kim and B. Kim, “A Sub-mW Fully Integrated Wide-Band Receiver for Wireless Sensor Network,” IEEE Microw. Wireless Compon. Lett., vol. 25, no. 5, pp. 319-321, May 2015.
[49] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 179-194, Feb. 1998.
[50] E. Hegazi and A. A. Abidi, “Varactor characteristics, oscillator tuning curves, and AM-FM conversion,” IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 1033-1039, June 2003.
[51] B. Soltanian and P. Kinget, “AM-FM conversion by the active devices in MOS LC-VCOs and its effect on the optimal amplitude,” in IEEE Radio Freq. Integr. Circuits Symp. (RFIC), San Francisco, CA, USA, 2006, pp. 4 pp.-108.
[52] J. Groszkowski, “The Interdependence of Frequency Variation and Harmonic Content, and the Problem of Constant-Frequency Oscillators,” Proc. IRE, vol. 21, no. 7, pp. 958-981, July 1933.
[53] A. Bevilacqua and P. Andreani, “On the bias noise to phase noise conversion in harmonic oscillators using Groszkowski theory,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), Rio de Janeiro, Brazil, 2011, pp. 217-220.
[54] D. Murphy, H. Darabi and H. Wu, “Implicit Common-Mode Resonance in LC Oscillators,” IEEE J. Solid-State Circuits, vol. 52, no. 3, pp. 812-821, March 2017.
[55] J. R. Long, “Monolithic transformers for silicon RF IC design,” IEEE J. Solid-State Circuits, vol. 35, no. 9, pp. 1368-1382, Sept. 2000.
[56] A. Goel and H. Hashemi, “Frequency Switching in Dual-Resonance Oscillators,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 571-582, March 2007.
[57] Y. Hu, T. Siriburanon and R. B. Staszewski, “A 30-GHz class-F23 oscillator in 28nm CMOS using harmonic extraction and achieving 120 kHz 1/f3 corner,” IEEE ESSCIRC, Leuven, Belgium, 2017, pp. 87-90.
[58] H. Guo, Y. Chen, P. -I. Mak and R. P. Martins, “A 0.083-mm2 25.2-to-29.5 GHz Multi-LC-Tank Class-F234 VCO With a 189.6-dBc/Hz FOM,” IEEE Solid-State Circuits Lett., vol. 1, no. 4, pp. 86-89, April 2018.
[59] Z. Wang, K. Ma, Z. Ma, H. Shi, H. Fu and J. Xu, “A Reconfigurable Injection-Locked LO Generator With a Wideband-Harmonic-Shaping Class-F23 VCO for Multibands 5G mm-Wave,” IEEE Trans. Microw. Theory Techn.
[60] H. -Y. Chang and Y. -T. Chiu, “K-Band CMOS Differential and Quadrature Voltage-Controlled Oscillators for Low Phase-Noise and Low-Power Applications,” IEEE Trans. Microw. Theory Techn., vol. 60, no. 1, pp. 46-59, Jan. 2012.
[61] H. Jia, B. Chi and Z. Wang, “An 8.2 GHz triple coupling low-phase-noise class-F QVCO in 65nm CMOS,” IEEE ESSCIRC, Graz, Austria, 2015, pp. 124-127.
[62] I. -S. Shen and C. F. Jou, “A X-Band Capacitor-Coupled QVCO Using Sinusoidal Current Bias Technique,” IEEE Trans. Microw. Theory Techn., vol. 60, no. 2, pp. 318-328, Feb. 2012.
[63] S. -Y. Lin and H. -K. Chiou, “A Modified High Phase Accuracy SIC-QVCO Using a Complementary-Injection Technique,” IEEE Microw. Wireless Compon. Lett., vol. 29, no. 3, pp. 222-224, March 2019.
[64] P. -Y. Wang, G. -Y. Su, Y. -C. Chang, D. -C. Chang and S. S. H. Hsu, “A low phase noise quadrature phase oscillator with frequency pulling suppression technique,” in IEEE MTT-S Int. Microw. Symp. Dig., Honololu, HI, USA, 2017, pp. 1145-1147.
[65] M. T. Amin, P. -I. Mak and R. P. Martins, “A 0.137 mm^2 9 GHz Hybrid Class-B/C QVCO With Output Buffering in 65 nm CMOS,” IEEE Microw. Wireless Compon. Lett., vol. 24, no. 10, pp. 716-718, Oct. 2014.
[66] Yin-Cheng Chang, Yuan-Chia Hsu, Shuw-Guann Lin, Ying-Zong Juang and Hwann-Kaeo Chiou, “On-wafer single contact quadrature accuracy measurement using receiver mode in four-port vector network analyzer,” IEEE MTT-S Int. Microwave Symp. Dig., Atlanta, GA, USA, 2008.
[67] H. O. Johansson, “A simple precharged CMOS phase frequency detector,” IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 295-299, Feb. 1998.
[68] W. Rhee, “Design of high-performance CMOS charge pumps in phase-locked 187 loops,” in Proc. IEEE Int. Symp. Circuits Syst., vol. 2, pp. 545-548, 1999-Jun.
[69] F. Xiangning, L. Bin, Y. Likai and W. Yujie, “CMOS Phase Frequency Detector and Charge Pump for Wireless Sensor Networks,” in IEEE MTT-S Int. Microw. Symp. Dig., Nanjing, China, 2012, pp. 1-4.
[70] J. Gong, E. Charbon, F. Sebastiano and M. Babaie, “A Low-Jitter and Low-Spur Charge-Sampling PLL,” IEEE J. Solid-State Circuits, vol. 57, no. 2, pp. 492-504, Feb. 2022.
[71] Y. Zhao, M. Forghani and B. Razavi, “A 20-GHz PLL With 20.9-fs Random Jitter,” IEEE J. Solid-State Circuits, vol. 58, no. 6, pp. 1597-1609, June 2023.
[72] J. -H. Tsai, C. -H. Chao and H. -D. Shih, “A X-band fully integrated CMOS frequency synthesizer,” in IEEE Asia–Pacific Microw. Conf., Kaohsiung, Taiwan, 2012, pp. 1226-1228.
[73] J. -H. Tsai, C. -Y. Hsu and C. -H. Chao, “An X-band 9.75/10.6 GHz low-power phase-locked loop using 0.18-μm CMOS technology,” in Proc. 10th Eur. Microw. Integr. Circuits Conf. (EuMIC), Paris, France, 2015, pp. 238-241.
[74] H. Alsuraisry, C. -H. Yim, J. -H. Cheng, J. -H. Tsai and T. -W. Huang, “A X-band frequency synthesizer for FMCW radar in 180-nm CMOS,” in IEEE Asia–Pacific Microw. Conf., Nanjing, China, 2015, pp. 1-3.
[75] 呂冠學，微波及毫米波倍頻器、多相位高功率高效率壓控振盪器及鎖相迴路之研製，國立中央大學電機工程研究所碩士論文，民國105年。

指導教授

張鴻埜

審核日期

2023-8-11

推文