3D快閃記憶體晶片測試平台開發

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姓名

李浩源(Hao-Yuan Lee) 查詢紙本館藏

畢業系所

資訊工程學系

論文名稱

3D快閃記憶體晶片測試平台開發
(Development of a Testing Platform for 3D Flash Memory Chips)

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至系統瀏覽論文 (2028-7-28以後開放)

摘要(中)

3D快閃記憶體晶片在容量和讀寫速度方面不斷提升，產品生命週期不斷縮短，這促使晶片製造商需要投入更多人力來縮短韌體開發及測試驗證時間。為此我們開發了一個用於3D快閃記憶體的測試平台，目的在於能夠根據待測晶片規格，自動產生並輸出韌體程式碼的功能指令以及測試流程的程式腳本，讓使用者得以快速進行功能指令的設定和記憶體特性分析，同時也確保了程式的開發效率和提升可靠性。此一平台可驗證TLC模式下基礎功能指令(如擦除、寫入、讀取、讀取重試)的正確性，同時可進行TLC、SLC以及TLC與SLC混用模式下的特性測試，並透過實驗來驗證不同模式下的耐久性。藉此平台，我們進行一系列的3D快閃記憶體的測試，在TLC模式下，當對WL0和WL1進行3,000次P/E操作後，讀取WL0直到發生致命錯誤時，相較於沒有Close WL的WL0，具有Close WL的WL1的讀取次數增加了1.23倍。此外，當P/E超過3000次後，無論是否有Close WL，在讀取WL0與WL1直到發生致命錯誤時，WL0的讀取次數整體上都高於WL1。這證明了P/E次數對於記憶體的讀取次數具有重要影響。以此驗證了我們所開發的3D快閃記憶體的測試平台的實用性。

摘要(英)

3D NAND flash memory chips have been continuously advancing in terms of capacity and read/write speed, leading to shorter product life cycles. This necessitates chip manufacturers to allocate more resources to reduce firmware development and testing/validation time. To address this, we have developed a testing platform specifically designed for 3D NAND flash memory. The platform aims to automatically generate and output firmware code for functional instructions and program scripts for test procedures based on the specifications of the target chip. This enables users to quickly configure functional instructions and analyze memory characteristics, while ensuring efficient program development and improved reliability. The platform verifies the correctness of basic functional instructions (such as erase, program, read, and read retry) in TLC mode and conducts feature testing in TLC, SLC, and mixed TLC/SLC modes. Additionally, it utilizes experiments to validate durability in different modes. Using this platform, we conducted a series of tests on 3D NAND flash memory. In TLC mode, after performing 3,000 P/E cycles on WL0 and WL1, the read count of WL1 with Close WL was found to be 1.23 times higher compared to WL0 without Close WL, until a fatal error occurred during read. Furthermore, beyond 3,000 P/E cycles, regardless of Close WL, the overall read count of WL0 was higher than WL1 when reading until a fatal error occurred. This demonstrates the significant impact of P/E cycles on the read count of the memory. These findings validate the practicality of the developed testing platform for 3D NAND flash memory.

關鍵字(中)

★ 快閃記憶體
★ 嵌入式硬體

關鍵字(英)

★ Flash memory
★ Embedded hardware

論文目次

摘要 I
Abstract II
誌謝 III
圖目錄 VIII
表目錄 XI
第一章、緒論 1
1.1 研究背景 1
1.2 研究目標 2
1.3 論文架構 3
第二章、技術回顧 4
2.1 快閃記憶體(Flash Memory)介紹 4
2.2 3D NAND快閃記憶體結構 5
2.3 3D NAND快閃記憶體操作原理 7
2.3.1 指令輸入週期(Command Input Cycle) 8
2.3.2 位址輸入週期(Address Input Cycle) 9
2.3.3 擦除操作(Erase) 9
2.3.4 寫入操作(Program) 10
2.3.5 讀取操作(Read) 11
2.3.6 讀取狀態(Read Status) 12
2.3.7 讀取重試(Read Retry) 13
2.4 3D NAND Flash錯誤修正碼ECC (Error Control Coding) 15
2.4.1 BCH(Bose Chaudhuri Hocquenghem)碼 16
2.4.2 LDPC(Low Density Parity Check)碼 16
2.5 3D NAND快閃記憶體晶片測試平台 17
第三章、快閃記憶體測試系統(FMTS)設計 18
3.1 系統設計方法論 18
3.1.1 階層式模組化架構 19
3.1.2 離散事件建模 20
3.2 FMTS設計 21
3.2.1 快閃記憶體操作功能指令模組A1 21
3.2.2 快閃記憶體錯誤偵測與修正模組A2 22
3.2.3 快閃記憶體讀取重試模組A3 22
3.3 快閃記憶體測試離散事件建模 22
3.3.1 記憶體操作功能指令 23
3.3.2 修正錯誤代碼功能模組 25
3.3.3 讀取重試功能模組 25
第四章、實驗結果 28
4.1 實驗環境 28
4.2 測試平台軟體架構 29
4.3 Multi-Plane TLC/SLC構造差異 31
4.4 Multi-Plane TLC記憶體操作功能指令實驗結果 31
4.4.1 TLC Erase實驗結果 31
4.4.2 TLC Program實驗結果 34
4.4.3 TLC Read實驗結果 37
4.4.4 TLC Read Retry實驗結果 40
4.4.5 TLC Read Fail實驗結果 45
4.5 Multi-Plane TLC/SLC P/E Cycle之特性測試實驗結果 46
4.5.1 TLC P/E Cycle之特性測試 47
4.5.2 SLC P/E Cycle之特性測試 50
4.5.3 TLC/SLC混用P/E Cycle之特性測試 52
第五章、結論與未來展望 54
5.1 結論 54
5.2 未來展望 55
參考文獻 56

參考文獻

[1] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, "Introduction to flash memory," Proceedings of the IEEE, vol. 91, no. 4, pp. 489-502, 2003.
[2] D. Liu, L. Yao, L. Long, Z. Shao, and Y. Guan, "A workload-aware flash translation layer enhancing performance and lifespan of TLC/SLC dual-mode flash memory in embedded systems," Microprocessors and Microsystems, vol. 52, pp. 343-354, 2017.
[3] M. Darnell, "Error control coding: Fundamentals and applications," in IEE Proceedings F-Communications, Radar and Signal Processing, vol. 1, no. 132, p. 68, 1985.
[4] Q. Li, Q. Wang, L. Yang, X. Yu, Y. Jiang, J. He, and Z. Huo, "Optimal read voltages decision scheme eliminating read retry operations for 3D NAND flash memories," Microelectronics Reliability, vol. 131, p. 114509, 2022.
[5] J.-D. Lee, S.-H. Hur, and J.-D. Choi, "Effects of floating-gate interference on NAND flash memory cell operation," IEEE Electron Device Letters, vol. 23, no. 5, pp. 264-266, 2002.
[6] N. Flash, "101: An introduction to NAND Flash and how to design it in to your next product," Micron, pp. 1-28, 2006.
[7] A. Goda, "Recent progress on 3D NAND flash technologies," Electronics, vol. 10, no. 24, p. 3156, 2021.
[8] X. Dong and Y. Xie, "AdaMS: Adaptive MLC/SLC phase-change memory design for file storage," in 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), pp. 31-36, 2011.
[9] Y. Cai, E. F. Haratsch, O. Mutlu, and K. Mai, "Threshold voltage distribution in MLC NAND flash memory: Characterization, analysis, and modeling," in 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1285-1290, 2013.
[10] H. Choi, W. Liu, and W. Sung, "VLSI implementation of BCH error correction for multilevel cell NAND flash memory," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 5, pp. 843-847, 2009.
[11] S. Wang, F. Wu, Z. Lu, Y. Zhou, Q. Xiong, M. Zhang, and C. Xie, "Lifetime adaptive ECC in NAND flash page management," in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, pp. 1253-1556, 2017.
[12] X. Zhang, J. Zhu, and Y. Wu, "Efficient one-pass Chase soft-decision BCH decoder for multi-level cell NAND flash memory," in 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1-4, 2011.
[13] J. Thorpe, "Low-density parity-check (LDPC) codes constructed from protographs," IPN progress report, vol. 42, no. 154, pp. 42-154, 2003.
[14] C.-H. Chen, M.-Y. Lin, and X.-C. Guo, "High-level modeling and synthesis of smart sensor networks for Industrial Internet of Things," Computers & Electrical Engineering, vol. 61, pp. 48-66, 2017.

指導教授

陳慶瀚(Ching-Han Chen)

審核日期

2023-7-25

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