準備好了嗎？ SE公司之EDA軟體工具先行者優勢路徑

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潘志豪(PAN, CHIH-HAO) 查詢紙本館藏

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高階主管企管碩士班

論文名稱

準備好了嗎？ SE公司之EDA軟體工具先行者優勢路徑

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摘要(中)

本論文旨在探討EDA軟體產業在半導體領域中，尤其是在靜電放電（ESD，Electro Static Discharge）和元件電氣過應力（EOS，Electrical Over Stress）以及可靠度分析(Reliability)方面的需求。我們通過專家訪談的方式，深入了解了SE公司Calibre PERC軟體作為科技先行者在這一領域取得成功的案例。這些軟體工具在半導體設計公司和晶圓代工廠之間的生態系統中扮演著至關重要的角色，可謂是半導體產業的中流砥柱，支撐著年產值數十萬億美元的產業。EDA軟體工具的創新開發旨在加速並簡化設計和驗證流程，而這些創新往往是基於晶片設計公司和晶圓代工廠的需求。因此EDA軟體產業可以被視為科技先行者，並且在眾多競爭對手中脫穎而出。
SE公司的Calibre PERC軟體工具被譽為科技先行者。這個軟體工具的創新概念是將SE公司在實體驗證領域的專業知識延伸至靜電放電和元件電氣過應力（ESD/EOS）以及可靠度分析的需求。這一創新概念的起源可以追溯到17至18年前，當時DFM（可製造性設計）的潮流興起，晶圓代工廠不斷開發新的工藝，但卻面臨著晶片設計量產中嚴重的良率問題。為了解決DFM相關的問題，EDA軟體工具廠商投入了大量資金進行創新解決方案的開發。由於SE公司在實體驗證領域(Physical Verificatin)佔有相當大的市場份額並且已經開發了設計可製造性(DFM)相關的解決方案，因此他們能夠重新開發其軟體工具，以滿足靜電放電和元件電氣過應力工程師的需求。這使得SE公司的PERC軟體工具能夠成功與晶圓代工廠合作，佔據市場份額。此外SE公司還在不斷開發創新，希望進一步擴大其軟體工具的影響力和市場份額，甚至擴展至晶圓代工廠的成熟工藝，以解決晶片設計公司的良率問題。

摘要(英)

This thesis aims to explore the demand for Electronic Design Automation (EDA) software in the semiconductor industry， particularly in the areas of Electrostatic Discharge (ESD)， Electrical Overstress (EOS)， and Reliability analysis。 Through expert interviews， we gain insights into the success of SE company′s Calibre PERC software as a technology leader in this field。 These software tools play a crucial role in the ecosystem between semiconductor design companies and wafer foundries， serving as a cornerstone of the semiconductor industry， which supports an annual production value of trillions of dollars。 The innovation and development of EDA software tools aim to accelerate and simplify the design and verification processes， often based on the needs of chip design companies and wafer foundries。 Therefore， the EDA software industry can be considered as a technology leader， standing out among numerous competitors。

SE company′s Calibre PERC software tool is recognized as a technology leader。 The innovative concept of this software tool extends SE company′s expertise in physical verification to meet the demands of Electrostatic Discharge (ESD)， Electrical Overstress (EOS)， and Reliability analysis。 The origin of this innovative concept can be traced back to 17-18 years ago when the trend of Design for Manufacturability (DFM) emerged。 Wafer foundries were continuously developing new processes， but faced serious yield issues during chip mass production。 To address DFM-related issues， EDA software tool vendors invested heavily in the development of innovative solutions。 Due to SE company′s significant market share in physical verification and their development of DFM-related solutions， they were able to redevelop their software tools to meet the needs of ESD/EOS engineers。 This enabled SE company′s PERC software tool to successfully collaborate with wafer foundries and capture market share。 Furthermore， SE company continues to innovate with the aim of expanding the influence and market share of its software tools， even extending to mature processes in wafer foundries to address yield issues for chip design companies。

關鍵字(中)

★ SE公司
★ 軟體工具
★ 半導體

關鍵字(英)

★ SE company
★ software tool
★ semiconductor

論文目次

圖目錄 vii
表目錄 ix
第一章緒論 1
1.1研究背景與動機 1
1.2研究目的 3
1.3研究流程 4
第二章文獻探討 5
2.1 EDA 軟體產業 5
2.1.1 EDA 產業的起源 5
2.1.2 EDA 產業的規模 7
2.1.3 EDA產業的未來 10
2.2 EDA 軟體工具 12
2.2.1 EDA 與晶圓代工廠及無晶圓IC設計公司的關係 13
2.2.2 EDA軟體工具提供的IC晶片設計流程 14
2.3 EDA 軟體工具之科技先行者概念 17
第三章研究方法 22
3.1研究架構 22
3.2 專家訪談對象的選擇 23
3.3 訪談準備 24
第四章個案公司分析與探討 26
4.1 個案公司介紹 26
4.2訪談問題選擇與訪談結果呈現 26
4.3訪談結果分析與討論 39
4.4 個案公司先行者模式分析 42
4.4.1 電路的拓樸檢查(Topology Check) 44
4.4.2 用人眼，標記層檢查還是用EDA軟體工具自動化檢查? 45
4.4.3 靜電放電電路擺放位置及放電路徑品質的檢查 47
4.4.4 特殊的DRC規則檢查 50
4.4.5 技術演進還是運氣 51
4.5亞太市場行銷方法與結果 54
4.6 管理意涵 55
第五章結論與建議 56
5.1研究總結 56
5.2研究管理意涵或建議 57
5.3研究限制 58
5.4未來研究方向 59

參考文獻

1.Arnaud, A., Fiorelli, R., & Galup-Montoro, C. (2006). Nanowatt, sub-nS OTAs, with sub-10-mV input offset, using series-parallel current mirrors. IEEE Journal of Solid-State Circuits, 41(9), 2009-2018.
2.Beg, A., & Ibrahim, W. (2009, June). Relating reliability to circuit topology. In 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (pp. 1-4). IEEE.
3.Bown, C. P. (2020). "Trump′s Trade War Timeline: An Up-to-Date Guide." Peterson Institute for International Economics. https://www.piie.com/research/piie-charts/trump-trade-war-china-date-guide
4.Lavagno, L., Scheffer, L., & Martin, G. (Eds.). (2018). EDA for IC implementation, circuit design, and process technology. CRC press.
5.Oruganti Sampath Srikar, O. The History of EDA and its Impact on the electronics industry. Medium. https://sampathsrikar.medium.com/the-history-of-eda-and-its-impact-on-the-electronics-industry81ddb5241bc6#:~:text=The%20Emergence%20of%20EDA%3A%20The%20term%20EDA%20was,made20the%20design%20process%20faster%20and%20more%20efficient
6.Lieberman, M. B., & Montgomery, D. B. (1988). First-Mover Advantages. Strategic Management Journal, 9(Special Issue: Strategy Content Research), 41–58.
7.Design for manufacturability. In Wikipedia. https://en.wikipedia.org/wiki/Design_for_manufacturability
8.Renesas. Understanding the Differences in ESD Device-Level Testing. https://www.renesas.com
9.EOS/ESD Association, Inc. EOS/ESD Fundamentals Part 5. https://www.esda.org
10.Embedded Computing Design. Fundamentals of HBM, MM, and CDM Tests. https://www.embeddedcomputing.com
11.Siemens EDA. Calibre PERC User’s Manual.
12.Siemens EDA. DFM Data Analysis User’s and Reference Manual.
13.Siemens EDA. Verification User’s Manual.
14.Siemens EDA. Standard Verification Rule Format (SVRF) Manual.
15.Voldman, S. H. (2016, October). Evolution and revolution of electrostatic discharge (ESD) and electrical overstress (EOS) testing for components and systems. In 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) (pp. 441–443). IEEE.
16.Durham, N. C. The Battle for Chips Semiconductors Crucial Role in AI Development and its Implications for US-China Strategic Competition.
17."U.S. Targets China′s Chip Industry." (2023, May 4). The Wall Street Journal. https://www.wsj.com/articles/u-s-targets-chinas-chip-industry-11696245666
18."U.S. Targets China′s Chip Industry." (2023, May 4). The Wall Street Journal. https://www.wsj.com/articles/u-s-targets-chinas-chip-industry-11696245666
19.He, L., Chen, C., & Huang, X. (2023). "The Impact of U.S.-China Trade Conflict on Global Supply Chains: Evidence from the Semiconductor Industry." Journal of International Economics, 126, 103462. https://doi.org/10.1016/j.jinteco.2020.103462
20.Kuhn, R. (2023, October 17). "The Chip Wars: How China Threatens US Dominance in Semiconductors." Council on Foreign Relations. https://www.cfr.org/backgrounder/chip-wars-how-china-threatens-us-dominance-semiconductors
21. Zhou, B. (2023). The Impact of the US Chip Act and the Chip4 Alliance, and China How to Respond It. Transactions on Social Science, Education and Humanities Research, 1, 407-410.
22. Flynn, C. (2020). Recommendations on export controls for artificial intelligence. Centre for Security and Emerging Technology.
23.Madakam, S., Ramaswamy, R., & Tripathi, S. (2015). Internet of Things (IoT): A literature review. Journal of Computer and Communications, 3(5), 164-173.
24. Thomas, D., & Moorby, P. (2008). The Verilog® hardware description language. Springer Science & Business Media.
25.Christen, E., & Bakalar, K. (1999). VHDL-AMS-a hardware description language for analog and mixed-signal applications. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 46(10), 1263-1272.
26.Kundert, K., Chang, H., Jefferies, D., Lamant, G., Malavasi, E., & Sendig, F. (2000). Design of mixed-signal systems-on-a-chip. IEEE transactions on computer-aided design of integrated circuits and systems, 19(12), 1561-1571.
27.Jurczak, M., Collaert, N., Veloso, A., Hoffmann, T., & Biesemans, S. (2009, October). Review of FINFET technology. In 2009 IEEE international SOI conference (pp. 1-4). IEEE.
28.Bae, G., Bae, D. I., Kang, M., Hwang, S. M., Kim, S. S., Seo, B., ... & Kang, H. K. (2018, December). 3nm GAA technology featuring multi-bridge-channel FET for low power and high performance applications. In 2018 IEEE International Electron Devices Meeting (IEDM) (pp. 28-7). IEEE.
29.Kim, Y., Kim, J., Kim, H., Lee, H., Kim, D., Seo, S. K., ... & Kim, D. W. (2023, May). Die to Wafer Hybrid Cu Bonding for Fine Pitch 3D-IC Applications. In 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC) (pp. 1043-1047). IEEE.
30. Lee, H. J., Mahajan, R., Sheikh, F., Nagisetty, R., & Deo, M. (2020, March). Multi-die integration using advanced packaging technologies. In 2020 IEEE Custom Integrated Circuits Conference (CICC) (pp. 1-7). IEEE.
31. Goel, S. K., Adham, S., Wang, M. J., Chen, J. J., Huang, T. C., Mehta, A., ... & Kim, S. (2013, September). Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study. In 2013 IEEE International Test Conference (ITC) (pp. 1-10). IEEE.
32.Lin, M. P. H., He, Y. T., Hsiao, V. W. H., Chang, R. G., & Lee, S. Y. (2013). Common-centroid capacitor layout generation considering device matching and parasitic minimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32(7), 991-1002.

指導教授

洪秀婉

審核日期

2024-5-14

推文