實現全後段製程相容性、基於IGZO雙電晶體及鐵電電容器之非揮發性記憶體

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蔡堉秭(Yu-Tzu Tsai) 查詢紙本館藏

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電機工程學系

論文名稱

實現全後段製程相容性、基於IGZO雙電晶體及鐵電電容器之非揮發性記憶體
(Enabling Fully Back-End-of-Line Compatible in IGZO Based Two Transistor One Ferroelectric Capacitor (2T1F) Non-Volatile Memory)

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摘要(中)

本研究將基於In-Ga-Zn-O(IGZO)之氧化物半導體電晶體(Oxide Semiconductor Field Effect Transistor)與採用HfO2/ZrO2層狀堆疊結構之金屬-鐵電-金屬(MFM)電容整合，展現了具後段製程兼容性潛力之雙電晶體單鐵電電容(2T1F)記憶體。我們使用兩個IGZO通道電晶體，作為寫入與讀取之電晶體，其展現了正臨界電壓且低遲滯現象，滿足元件之非揮發性與可靠度之需求，並整合低退火溫度之鐵電製程開發(≦400°C)，使其具備後段製程兼容性。該結構經由調節鐵電電容與讀取電晶體之間的面積比例(Area Ratio (AR) = AMFM/Atransistor)，使記憶窗口達到2.5V；在耐久性測試中，該元件在操作電壓1.5V下，經過106次讀寫循環測試後仍保有足夠的記憶窗口。該研究不僅實現了具後段製程兼容性的大記憶窗口與低操作電壓的技術，還展示了其在高密度、低功耗記憶體設計中的應用潛力，這對於未來需要大量數據處理與儲存的人工智能(AI)運算和記憶功能有重要的推動作用。

摘要(英)

This study successfully integrates an oxide semiconductor field-effect transistor (OSFET) based on In-Ga-Zn-O (IGZO) with a Metal-Ferroelectric-Metal (MFM) capacitor using an HfO2/ZrO2 layered stack structure, achieving a back-end-of-line (BEOL) compatible two-transistor-one-capacitor (2T1F) ferroelectric memory. Utilizing two IGZO channel transistors for writing and reading, which exhibit positive threshold voltages and low hysteresis, fulfills the requirements for non-volatility and reliability. The integration involves a low annealing temperature ferroelectric process (?400°C), ensuring back-end-of-line compatibility. By tuning the area ratio (AR = AMFM/Atransistor) between the ferroelectric capacitor and the readout transistor, a memory window of 2.5V was attained. In endurance testing, the device retained a sufficient memory window after 106 read/write cycles at an operating voltage of 1.5V.
This research not only demonstrates a BEOL-compatible technology with a large memory window and low operating voltage, but also reveals its potential in high-density, low-power memory designs. This is expected to significantly advance future artificial intelligence (AI) computation and memory functions that require extensive data processing and storage capabilities.

關鍵字(中)

★ 鐵電記憶體
★ 氧化物半導體

關鍵字(英)

論文目次

目錄
摘要……………………………………………………………………………………i
Abstract………………………………………………………………………………ii
致謝…………………………………………………………………………………iii
目錄…………………………………………………………………………………v
圖目錄………………………………………………………………………………vi
第一章序論與文獻回顧 1
1.1鐵電(Ferroelectricity) 1
1.1.1傳統鐵電材料 1
1.1.2 氧化鉿鋯鐵電薄膜(HfxZr1-xO2,HZO) 2
1.1.3 鐵電極化機制 3
1.2鐵電材料在非揮發性記憶體中的應用 4
1.2.1 FeRAM 4
1.2.2 FeFET 5
1.2.3 MFMFET 6
1.3基於鐵電材料之記憶體面臨的問題 7
1.3.1 微縮性(Scalability) 7
1.3.2 熱預算(Thermal Budget) 8
1.3.3 耐久性(Endurance) 8
1.3.4 資料保留度(data retention) 9
1.4新型結構鐵電記憶體 10
1.4.1 3D結構鐵電記憶體 11
1.4.2 2T1C鐵電記憶體 11
1.5氧化物半導體通道(Oxide Semiconductor Channel) 13
1.5.1氧化物半導體的特性 13
1.5.1氧化物半導體的2T1C的整合可能性 13
第二章實驗製程 33
2.1 製程流程 33
2.2 薄膜製程 33
2.3 熱退火處理 34
2.4 黃光製程 34
2.5 蝕刻製程 34
2.6 金屬導線連接 35
第三章 2T1F記憶體之操作與量測 42
3.1 元件架構及量測設置 42
3.2 寫入操作 42
3.3 讀取操作 43
3.4 資料保留度量測 43
3.5 耐久性量測 43
第四章結果與討論 50
4.1 HZO鐵電電容 50
4.2 IGZO通道電晶體 51
4.3 記憶窗口(Memory window) 52
4.3.1 面積比例調變的影響 52
4.3.2 不同寫入電壓之分析 53
4.3.3 不同讀取電壓之分析 53
4.4 資料保留度 54
4.5 耐久性 55
第五章結論與未來展望 66
參考文獻 67
附錄 77

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ACS Applied Materials & Interfaces, 2022 14 (45), 51137-51148.

指導教授

唐英瓚(Ying-Tsan Tang)

審核日期

2024-11-26

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