針對STT-MRAM記憶體內運算架構在電路老化和溫度變化的情況之下達成延長使用壽命的目標

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：110

、訪客IP：18.220.116.34

姓名

林宜霆(Yi-Ting Lin) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

針對STT-MRAM記憶體內運算架構在電路老化和溫度變化的情況之下達成延長使用壽命的目標
(Empowering Longevity: A Resilient STT-MRAM Computing-In-Memory Architecture Tackling Circuit Aging and Temperature Variations)

相關論文

★ 晶圓圖之網格及稀疏缺陷樣態辨識	★ 晶圓圖提取特徵參數錯誤樣態分析
★ 使用聚類過濾策略和 CNN 計算識別晶圓圖瑕疵樣態	★ 新建晶圓圖相似性門檻以強化相似程度辨別能力
★ 一種可動態重新配置的4:2近似壓縮器用於補償老化	★ 一個可靠的靜態隨機存取記憶體內運算結構: 設計指南與耐老化策略研究
★ 一個高效的老化偵測器部屬策略: 基於生成對抗網路的設計方法	★ 考慮電壓衰退和繞線影響以優化電路時序之電源供應網絡精煉策略
★ 適用於提高自旋轉移力矩式磁阻隨機存取記憶體矩陣可靠度之老化偵測與緩解架構設計	★ 8T 靜態隨機存取記憶體之內積運算引擎的老化威脅緩解策略: 從架構及運算角度來提出解決的方法
★ 用於響應穩定性的老化感知平行掃描鏈PUF設計	★ 8T靜態隨機存取記憶體運算的老化檢測和容忍機制：適用於邏輯和 MAC 運算的應用
★ 使用擺置後的設計特徵及極限梯度提升演算法預測繞線後的繞線需求	★ 基於強化學習的晶片佈局規劃的卷積神經網路與圖神經網路融合架構
★ 用於佈線後階段電壓降優化的強化學習框架	★ 多核心系統的老化與瞬態錯誤感知任務部署策略：壽命延長且節能的框架

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

至系統瀏覽論文 (2029-7-16以後開放)

摘要(中)

自旋轉移矩磁阻式隨機存取記憶體（Spin-Transfer-Torque Magnetic Random-Access Memory, STT-MRAM）在新興記憶體中具有顯著的潛力。然而，除了會遭遇因老化引起的磁穿隧接面（Magnetic Tunnel Junction, MTJ）中時間依賴介電擊穿（Time-dependent Dielectric Breakdown, TDDB）的問題之外，在溫度變化時也會使流經MTJ的電流大小不一，導致錯誤產生與可靠度下降。這些現象在STT-MRAM記憶體內運算（In-Memory Computing, IMC）的模式中更為嚴重。為了解決這些挑戰，本文提出了一個具有熱感知能力的早期老化檢測和補償架構，在運算模式下監控記憶體運算的結果，並在檢測出有老化的可能性後予以補償。
我們的框架引入了幾個關鍵創新。首先，我們使用平行（Parallel, P）狀態的MTJ，調整感測放大器中參考產生器，以正確的運算邏輯AND與OR。其次，它具有早期老化檢測機制，同樣也是於參考產生器中使用P狀態MTJ，實時識別老化問題並記錄在查找表（Lookup Table, LUT）中以便補償。第三，我們設計了老化容忍機制，當在LUT中檢測到地址時，會透過調整運算單元進入感測放大器的電流來抵消由老化引起的電流上升。接著，我們主要都是以P狀態MTJ來做設計，包含參考產生器中的參考值以及使用P-P狀態檢測早期老化，有效地減輕了熱效應並防止相關錯誤。最後，我們的框架提供了即時且高效的解決方案，提高記憶體系統的可靠度和壽命。通過早期檢測老化和補償，解決由於老化和溫度變化導致的準確性下降，確保了穩定的STT-MRAM記憶體內運算。

摘要(英)

Spin-Transfer-Torque Magnetic Random-Access Memory (STT-MRAM) holds significant promise for on-chip memory, yet faces pronounced challenges arising from time-dependent dielectric breakdown (TDDB) of aging effects and thermal effects in the magnetic tunnel junction (MTJ). This phenomenon introduces concerns of endurance degradation and defect formation, particularly impactful in the context of In-Memory Computing (IMC) with STT-MRAM. This paper proposes a comprehensive early aging detection and tolerance framework with thermal awareness to address these challenges, designed to dynamically monitor memory cells during computing modes.
Our framework introduces several key innovations. First, we designed the reference generator of the sense amplifier in Parallel (P) state MTJ to compute the logic AND and OR operations correctly. Second, we proposed an early aging detection mechanism that utilizes P state MTJ in the reference generator to identify aging issues in real-time, recording in a Lookup Table (LUT) for tolerance. Third, we developed an aging tolerance mechanism that activates upon detecting addresses in the LUT, adjusting the current of the computing cells to counteract the current enhancement caused by aging, instead of the adjustment of the reference generator. Next, our design mostly used the P-state MTJ, including the reference in the reference generator and the P-P state early aging detection, effectively mitigating thermal effects and preventing related errors. Finally, our framework provides a real-time and efficient solution that enhances the reliability and lifetime of the memory system. By enabling early detection and compensation for aging, we address the accuracy degradation caused by aging and temperature variations, ensuring stable in-memory computing with STT-MRAM.

關鍵字(中)

★ 自旋轉移矩磁阻式隨機存取記憶體
★ 記憶體內運算
★ 老化偵測
★ 老化容忍
★ 溫度變化

關鍵字(英)

★ Spin-Transfer-Torque Magnetic Random-Access Memory, STT-MRAM
★ In-Memory Computing, IMC
★ Aging Detection
★ Aging Tolerance
★ Temperature Variations

論文目次

摘要 ii
Abstract iii
致謝 iv
Table of Contents v
Table of Figures vii
Table of Tables ix
Chapter 1 Introduction 1
1.1 The Necessities for Reliable and High Memory Devices 1
1.2 Fundamental of STT-MRAM 2
1.3 STT-MRAM-Based CIM 5
1.4 Reliability Issues of STT-MRAM 7
1.4.1 Aging Effect on MTJ 7
1.4.2 Thermal Effect on MTJ 9
1.4.3 Reliability Issues on STT-MRAM-Based CIM 11
1.5 Contributions 12
Chapter 2 Preliminaries 14
2.1 MTJ Defect Model 14
2.2 Previous Works 15
Chapter 3 Problem Formulation 18
3.1 Assumptions 18
3.2 Formulation 19
Chapter 4 Proposed Frameworks 20
4.1 Framework Overview 20
4.2 Sense Amplifier Mechanism 23
4.3 Computing Mechanism 24
4.4 Thermal Awareness Mechanism 26
4.5 Aging Detection and Aging Tolerance Mechanism 31
4.6 Lookup Table Design 35
Chapter 5 Experimental Results 38
5.1 Simulation Results of Logic Operations 39
5.2 Simulation Results of Aging Detection and Aging Tolerance Mechanism 40
Chapter 6 Conclusions 52
References 53

參考文獻

[1] Zhao, W., & Prenat, G. (2015). Spintronics-Based Computing. Berlin: Springer International Publishing.
[2] Zhao, W., Zhao, X., Zhang, B., et al. (2016). Failure Analysis in Magnetic Tunnel Junction Nanopillar with Interfacial Perpendicular Magnetic Anisotropy. Materials (Basel), 9(1), 41.
[3] Wang, Y., et al. (2014). Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses. Microelectronics Reliability, 54(9-10), 1774-1778.
[4] Wang, Y., et al. (2016). Compact model of dielectric breakdown in spin-transfer torque magnetic tunnel junction. IEEE Transactions on Electron Devices, 63(4), 1762-1767.
[5] Radhakrishnan, G., Yoon, Y., & Sachdev, M. (2020). Monitoring Aging Defects in STT-MRAMs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(12), 4645-4656.
[6] Khvalkovskiy, A.V., et al. (2013). Basic principles of STT-MRAM cell operation in memory arrays. Journal of Physics D: Applied Physics, 46, 1-7.
[7] Oliver, B., et al. (2004). Two breakdown mechanisms in ultrathin alumina barrier magnetic tunnel junctions. Journal of Applied Physics, 95(3), 1315-1322.
[8] Hua, L., et al. (2018). Barrier breakdown mechanism in nano-scale perpendicular magnetic tunnel junctions with ultrathin MgO barrier. AIP Advances, 8(5), 055908.
[9] Panagopoulos, G., Augustine, C., & Roy, K. (2011). Modeling of dielectric breakdown-induced time-dependent STT-MRAM performance degradation. In 69th Device Research Conference (pp. 125-126).
[10] Ho, C.-H., Panagopoulos, G.D., Kim, S.Y., Kim, Y., Lee, D., & Roy, K. (2013). A physical model to predict STT-MRAM performance degradation induced by TDDB. In 71st Device Research Conference (pp. 59-60).
[11] Wu, L., et al. (2019). Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing. In 2019 IEEE European Test Symposium (ETS) (pp. 1-6).
[12] Joshi, V.K., Barla, P., Bhat, S., & Kaushik, B.K. (2020). From MTJ Device to Hybrid CMOS/MTJ Circuits: A Review. IEEE Access, 8, 194105-194146.
[13] Wu, L., Taouil, M., Rao, S., Marinissen, E.J., & Hamdioui, S. (2018). Electrical Modeling of STT-MRAM Defects. In 2018 IEEE International Test Conference (ITC) (pp. 1-10).
[14] McPherson, J.W., & Mogul, H.C. (1998). Underlying physics of the thermochemical E model in SiO2 describing low-field time-dependent dielectric breakdown in thin films. Journal of Applied Physics, 84(3), 1513-1523.
[15] Girard, P., Cheng, Y., Virazel, A., Zhao, W., Bishnoi, R., & Tahoori, M.B. (2021). A Survey of Test and Reliability Solutions for Magnetic Random Access Memories. Proceedings of the IEEE, 109(2), 149-169.
[16] Lin, I.-C., Law, Y.K., & Xie, Y. (2018). Mitigating BTI-Induced Degradation in STT-MRAM Sensing Schemes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(1), 50-62.
[17] Van Beek, S., et al. (2015). Four point probe ramped voltage stress as an efficient method to understand breakdown of STT-MRAM MgO tunnel junctions. In 2015 IEEE International Reliability Physics Symposium (pp. MY.4.1-MY.4.6).
[18] Zhou, Y., Cai, H., Zhang, M., Naviner, L.A.B., & Yang, J. (2020). A novel BIST for monitoring aging/temperature by self-triggered scheme to improve the reliability of STT-MRAM. Microelectronics Reliability, 114, 113735.
[19] Deak, J.G., Daughton, J.M., & Pohm, A.V. (2006). Effect of Resistance-Area-Product and Thermal Environment on Writing of Magneto-Thermal MRAM. IEEE Transactions on Magnetics, 42(10), 2721-2723.
[20] Liand, S., & Jiang, Y. (2022). Nanoscale Thermal Transport Model of Magnetic Tunnel Junction (MTJ) Device for STT-MRAM. IEEE Transactions on Magnetics, 58(8), 1-6, Art no. 3401206.
[21] Deschenes, A., Muneer, S., Akbulut, M., Gokirmak, A., & Silva, H. (2016). Analysis of self-heating of thermally assisted spin-transfer torque magnetic random access memory. Beilstein Journal of Nanotechnology, 7, 1676-1683.
[22] Teso, B., Siritaratiwat, A., & Surawanitkun, C. (2018). Different Effect of Temperature Increment on CoFeB/MgO Based Single and Double Barrier Magnetic Tunnel Junctions during Switching Process in STT-MRAM. In 2018 15th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON) (pp. 616-619).
[23] Zhang, X., et al. (2020). Life-time degradation of STT-MRAM by self-heating effect with TDDB model. Solid-State Electronics, 173, 107878.
[24] Chen, Y.-G., Huang, P.-Y., & Li, J.-F. (2023). An On-line Aging Detection and Tolerance Framework for Improving Reliability of STT-MRAMs. In 2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC) (pp. 1-6).
[25] Jain, S., Ranjan, A., Roy, K., & Raghunathan, A. (2018). Computing in Memory With Spin-Transfer Torque Magnetic RAM. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(3), 470-483.
[26] Cai, H., et al. (2023). 33.4 A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference. In 2023 IEEE International Solid-State Circuits Conference (ISSCC) (pp. 500-502).
[27] Wang, C., Wang, Z., Wang, G., Zhang, Y., & Zhao, W. (2021). Design of an Area-Efficient Computing in Memory Platform Based on STT-MRAM. IEEE Transactions on Magnetics, 57(2), 1-4, Art no. 3400504.
[28] Cai, H., et al. (2022). Proposal of Analog In-Memory Computing With Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell. IEEE Transactions on Circuits and Systems I: Regular Papers, 69(4), 1519-1531.
[29] Na, T., Kang, S.H., & Jung, S.-O. (2021). STT-MRAM Sensing: A Review. IEEE Transactions on Circuits and Systems II: Express Briefs, 68(1), 12-18.
[30] Pham, T.-N., Trinh, Q.-K., Chang, I.-J., & Alioto, M. (2022). STT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural Networks. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 12(2), 569-579.

指導教授

陳聿廣(Yu-Guang Chen)

審核日期

2024-9-20

推文